公开(公告)号：US11614422B2

公开(公告)日：2023-03-28

申请号：US17135508

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jie Huang ,  Jui-Cheng Huang ,  Cheng-Hsiang Hsieh

IPC: G01N27/414

Abstract: A biologically sensitive field effect transistor includes a substrate, a first control gate and a second control gate. The substrate has a first side and a second side opposite to the first side, a source region and a drain region. The first control gate is disposed on the first side of the substrate. The second control gate is disposed on the second side of the substrate. The second control gate includes a sensing film disposed on the second side of the substrate. A voltage biasing between the source region and the second control gate is smaller than a threshold voltage of the second control gate.

公开(公告)号：US20190145927A1

公开(公告)日：2019-05-16

申请号：US16227646

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jie HUANG ,  Jui-Cheng Huang ,  Cheng-Hsiang Hsieh

IPC: G01N27/414

Abstract: A biologically sensitive field effect transistor includes a substrate, a first control gate and a second control gate. The substrate has a first side and a second side opposite to the first side, a source region and a drain region. The first control gate is disposed on the first side of the substrate. The second control gate is disposed on the second side of the substrate. The second control gate includes a sensing film disposed on the second side of the substrate. A voltage biasing between the source region and the second control gate is smaller than a threshold voltage of the second control gate.

公开(公告)号：US10158364B1

公开(公告)日：2018-12-18

申请号：US15882544

申请日：2018-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsien Tsai ,  Cheng-Hsiang Hsieh ,  Chih-Hsien Chang ,  Ruey-Bin Sheen

IPC: H03L7/087 ,  H03L7/099 ,  H03L7/089 ,  H03B5/24 ,  H03K3/03

Abstract: A circuit having a tracking loop and a realignment loop is disclosed. The circuit includes: a phase frequency detector (PFD) module for comparing a phase difference of a first input signal and a second input signal; a pump module for converting PFD phase error to charge, wherein the pump module further comprises a low pass filter (LPF); an adjustable realignment module for adjusting a realignment strength, the adjustable realignment module receives a first plurality of inputs from the PFD module, the adjustable realignment module transmits a second plurality of outputs to the pump module; and a ring oscillator unit, the ring oscillator unit receives a first input from the pump module and a second input from the adjustable realignment module, and based on the first and second inputs produces a feedback signal.

公开(公告)号：US20220263537A1

公开(公告)日：2022-08-18

申请号：US17734920

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang LAN ,  Cheng-Hsiang Hsieh

IPC: H04B1/7085 ,  H04L7/00

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

公开(公告)号：US10516385B2

公开(公告)日：2019-12-24

申请号：US15475258

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsien Tsai ,  Ruey-Bin Sheen ,  Chih-Hsien Chang ,  Cheng-Hsiang Hsieh

IPC: H03K3/03

Abstract: A ring oscillator is provided. The ring oscillator includes a pseudo pass-gate inverter, a third transistor, a fourth transistor and a delay chain. The pseudo pass-gate inverter includes a first transistor and a second transistor in series. The third transistor is connected in series with the pseudo pass-gate inverter. The drain of the fourth transistor is connected to an output of the pseudo pass-gate inverter. The gate of the fourth transistor is connected to the gate of the third transistor to receive the realignment signal. The delay chain includes a plurality of delay cells. An input of the delay chain is connected to the output of the pseudo pass-gate inverter. When the realignment signal is in a realignment state, the third transistor is turned off, the fourth transistor is turned on.

公开(公告)号：US11356140B2

公开(公告)日：2022-06-07

申请号：US17320568

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang Lan ,  Cheng-Hsiang Hsieh

IPC: H04L7/02 ,  H04B1/7085 ,  H04L7/00

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

公开(公告)号：US11025294B2

公开(公告)日：2021-06-01

申请号：US16742423

申请日：2020-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang Lan ,  Cheng-Hsiang Hsieh

IPC: H04B1/7085 ,  H04L7/00

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

公开(公告)号：US10855292B2

公开(公告)日：2020-12-01

申请号：US16723205

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Kuei Kuan ,  Cheng-Hsiang Hsieh ,  Chen-Ting Ko ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: H03L7/089 ,  H03K7/08 ,  H03L7/091 ,  H03L7/099 ,  H03L7/093 ,  H03L7/087 ,  H03L7/097

Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

公开(公告)号：US10833660B2

公开(公告)日：2020-11-10

申请号：US16716910

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsien Tsai ,  Ruey-Bin Sheen ,  Chih-Hsien Chang ,  Cheng-Hsiang Hsieh

IPC: H03K3/03

Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.

公开(公告)号：US10523221B2

公开(公告)日：2019-12-31

申请号：US16189482

申请日：2018-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsien Tsai ,  Chih-Hsien Chang ,  Ruey-Bin Sheen ,  Cheng-Hsiang Hsieh

IPC: H03L7/093 ,  H03L7/099 ,  H03L7/085 ,  H03L7/087 ,  H03L7/113 ,  H03L7/183

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.