公开(公告)号：US20190173516A1

公开(公告)日：2019-06-06

申请号：US16261376

申请日：2019-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang LAN ,  Cheng-Hsiang Hsieh

IPC: H04B1/7085 ,  H04L7/00

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

公开(公告)号：US20210273674A1

公开(公告)日：2021-09-02

申请号：US17320568

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang LAN ,  Cheng-Hsiang HSIEH

IPC: H04B1/7085 ,  H04L7/00

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

公开(公告)号：US20220263537A1

公开(公告)日：2022-08-18

申请号：US17734920

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang LAN ,  Cheng-Hsiang Hsieh

IPC: H04B1/7085 ,  H04L7/00

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

公开(公告)号：US20200153478A1

公开(公告)日：2020-05-14

申请号：US16742423

申请日：2020-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang LAN ,  Cheng-Hsiang HSIEH

IPC: H04B1/7085 ,  H04L7/00

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

公开(公告)号：US20190058500A1

公开(公告)日：2019-02-21

申请号：US15938264

申请日：2018-03-28

Applicant: Taiwan Semiconductor manufacturing Co.,Ltd.

Inventor： Po-Hsiang LAN ,  Cheng-Hsiang HSIEH

IPC: H04B1/7085 ,  H04L7/00

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.