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公开(公告)号：US20210263022A1
公开(公告)日：2021-08-26
申请号：US17314825
申请日：2021-05-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jui-Cheng HUANG , Chin-Hua WEN , Tung-Tsun CHEN , Cheng-Hsiang HSIEH , Yu-Jie HUANG , Ching-Hui LIN
IPC: G01N33/543 , G01N27/416 , G01N27/414 , B01L3/00 , C12Q1/6837
Abstract: A fluidic cartridge and methods of operation are described. The fluidic cartridge includes a substrate having a plurality of contact pads designed to electrically couple with an analyzer, a semiconductor chip having a sensor array, and a reference electrode. The fluidic cartridge includes a first fluidic channel having an inlet and coupled to a second fluidic channel, the second fluidic channel being aligned such that the sensor array and the reference electrode are disposed within the second fluidic channel. A first plug is disposed at the first inlet. The first plug includes a compliant material configured to be punctured by a capillary without leaking fluid through the first plug.
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公开(公告)号：US20210148856A1
公开(公告)日：2021-05-20
申请号：US17135508
申请日：2020-12-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jie HUANG , Jui-Cheng HUANG , Cheng-Hsiang HSIEH
IPC: G01N27/414
Abstract: A biologically sensitive field effect transistor includes a substrate, a first control gate and a second control gate. The substrate has a first side and a second side opposite to the first side, a source region and a drain region. The first control gate is disposed on the first side of the substrate. The second control gate is disposed on the second side of the substrate. The second control gate includes a sensing film disposed on the second side of the substrate. A voltage biasing between the source region and the second control gate is smaller than a threshold voltage of the second control gate.
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公开(公告)号：US20180302096A1
公开(公告)日：2018-10-18
申请号：US15490096
申请日：2017-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ting-Kuei KUAN , Cheng-Hsiang HSIEH , Chen-Ting KO , Ruey-Bin SHEEN , Chih-Hsien CHANG
CPC classification number: H03L7/0891 , H03K7/08 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/097 , H03L7/099
Abstract: Track-and-hold charge pumps and PLL are provided. A track-and-hold charge pump includes a track-and-hold circuit, a transconductance amplifier, a pulse width modulator (PWM), and a pumping switch coupled to the transconductance amplifier. The track-and-hold circuit samples an input signal according to a reference clock. The transconductance amplifier converts the sampled input signal into a current. The PWM provides a PWM signal according to the reference clock. The pumping switch is controlled by the PWM signal, to provide an output current according to the current.
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公开(公告)号：US20170160226A1
公开(公告)日：2017-06-08
申请号：US14961588
申请日：2015-12-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yu-Jie HUANG , Jui-Cheng HUANG , Cheng-Hsiang HSIEH
IPC: G01N27/414
CPC classification number: G01N27/4145 , G01N27/4148
Abstract: A biologically sensitive field effect transistor includes a substrate, a first control gate and a second control gate. The substrate has a first side and a second side opposite to the first side, a source region and a drain region. The first control gate is disposed on the first side of the substrate. The second control gate is disposed on the second side of the substrate. The second control gate includes a sensing film disposed on the second side of the substrate. A voltage biasing between the source region and the second control gate is smaller than a threshold voltage of the second control gate.
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公开(公告)号：US20240421194A1
公开(公告)日：2024-12-19
申请号：US18336382
申请日：2023-06-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-An LAI , Pan Chieh Yu , Chih-Hua WANG , Chan-Hong CHERN , Cheng-Hsiang HSIEH
IPC: H01L29/20 , H01L29/40 , H01L29/66 , H01L29/778
Abstract: The present disclosure describes a semiconductor device having artificial field plates. The semiconductor device includes a first gallium nitride (GaN) layer on a substrate, an aluminum gallium nitride (AlGaN) layer on the first GaN layer, and a second GaN layer on the AlGaN layer. The first and second GaN layers includes different types of dopants. The semiconductor device further includes a gate contact structure in contact with the second GaN layer, first and second source/drain (S/D) contact structures in contact with the AlGaN layer, one or more artificial field plates between the gate contact structure and the first S/D contact structure. The first and second S/D contact structures are disposed at opposite sides of the gate contact structure. The one or more artificial field plates are separated from the first and second S/D contact structures and above the AlGaN layer.
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Patent Agency Ranking
公开(公告)号：US20230251223A1
公开(公告)日：2023-08-10
申请号：US18126577
申请日：2023-03-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jie HUANG , Jui-Cheng HUANG , Cheng-Hsiang HSIEH
IPC: G01N27/414
CPC classification number: G01N27/4145 , G01N27/4148
Abstract: A biologically sensitive field effect transistor includes a substrate, a first control gate and a second control gate. The substrate has a first side and a second side opposite to the first side, a source region and a drain region. The first control gate is disposed on the first side of the substrate. The second control gate is disposed on the second side of the substrate. The second control gate includes a sensing film disposed on the second side of the substrate. A voltage biasing between the source region and the second control gate is smaller than a threshold voltage of the second control gate.
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公开(公告)号：US20200127648A1
公开(公告)日：2020-04-23
申请号：US16716910
申请日：2019-12-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Hsien TSAI , Ruey-Bin SHEEN , Chih-Hsien CHANG , Cheng-Hsiang HSIEH
IPC: H03K3/03
Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.
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公开(公告)号：US20200091919A1
公开(公告)日：2020-03-19
申请号：US16689719
申请日：2019-11-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Hsien TSAI , Chih-Hsien CHANG , Ruey-Bin SHEEN , Cheng-Hsiang HSIEH
Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.
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公开(公告)号：US20180287593A1
公开(公告)日：2018-10-04
申请号：US15475258
申请日：2017-03-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Hsien TSAI , Ruey-Bin SHEEN , Chih-Hsien CHANG , Cheng-Hsiang HSIEH
IPC: H03K3/03
CPC classification number: H03K3/0315
Abstract: A ring oscillator is provided. The ring oscillator includes a pseudo pass-gate inverter, a third transistor, a fourth transistor and a delay chain. The pseudo pass-gate inverter includes a first transistor and a second transistor in series. The third transistor is connected in series with the pseudo pass-gate inverter. The drain of the fourth transistor is connected to an output of the pseudo pass-gate inverter. The gate of the fourth transistor is connected to the gate of the third transistor to receive the realignment signal. The delay chain includes a plurality of delay cells. An input of the delay chain is connected to the output of the pseudo pass-gate inverter. When the realignment signal is in a realignment state, the third transistor is turned off, the fourth transistor is turned on.
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公开(公告)号：US20250063824A1
公开(公告)日：2025-02-20
申请号：US18450475
申请日：2023-08-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Lin-Yu HUANG , Shih-Fan CHEN , Sheng-Fu HSU , Yi-An LAI , Chan-Hong CHERN , Cheng-Hsiang HSIEH
Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.
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