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    FULL RANGE REALIGNMENT RING OSCILLATOR
    1.
    发明申请
    FULL RANGE REALIGNMENT RING OSCILLATOR 审中-公开

    公开(公告)号：US20190165769A1

    公开(公告)日：2019-05-30

    申请号：US15826910

    申请日：2017-11-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsien TSAI ,  Chen-Hsiang Hsieh ,  Ruey-Bin SHEEN ,  Chih-Hsien CHANG

    IPC: H03K3/03 ,  H03K3/356 ,  H03L7/099 ,  H03L7/087 ,  H03L7/081

    Abstract: A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate. A drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate.

    PHASE LOCKED LOOP
    2.
    发明申请
    PHASE LOCKED LOOP 审中-公开

    公开(公告)号：US20200127668A1

    公开(公告)日：2020-04-23

    申请号：US16723205

    申请日：2019-12-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ting-Kuei KUAN ,  Cheng-Hsiang HSIEH ,  Chen-Ting KO ,  Ruey-Bin SHEEN ,  Chih-Hsien CHANG

    IPC: H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/091 ,  H03K7/08 ,  H03L7/097 ,  H03L7/087

    Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

    Hybrid Phase Lock Loop
    3.
    发明申请
    Hybrid Phase Lock Loop 审中-公开

    公开(公告)号：US20180152192A1

    公开(公告)日：2018-05-31

    申请号：US15428841

    申请日：2017-02-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsien TSAI ,  Ruey-Bin SHEEN ,  Chih-Hsien CHANG ,  Cheng-Hsiang HSIEH

    IPC: H03L7/099 ,  H03L7/085

    CPC classification number: H03L7/0991 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/183 ,  H03L2207/06

    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

    HYBRID PHASE LOCK LOOP
    4.
    发明申请
    HYBRID PHASE LOCK LOOP 审中-公开

    公开(公告)号：US20190158102A1

    公开(公告)日：2019-05-23

    申请号：US16189482

    申请日：2018-11-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsien TSAI ,  Chih-Hsien CHANG ,  Ruey-Bin SHEEN ,  Cheng-Hsiang HSIEH

    IPC: H03L7/099 ,  H03L7/113 ,  H03L7/183 ,  H03L7/085 ,  H03L7/087

    CPC classification number: H03L7/0991 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/183 ,  H03L2207/06

    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

    METHOD AND APPARATUS FOR PRECISION PHASE SKEW GENERATION
    8.
    发明申请
    METHOD AND APPARATUS FOR PRECISION PHASE SKEW GENERATION 有权

    公开(公告)号：US20220131536A1

    公开(公告)日：2022-04-28

    申请号：US17571227

    申请日：2022-01-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mao-Hsuan CHOU ,  Ya-Tin CHANG ,  Ruey-Bin SHEEN ,  Chih-Hsien CHANG

    IPC: H03K5/14 ,  H03L7/089 ,  H03K5/135

    Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

    RING OSCILLATOR, CONTROLLING CIRCUIT AND METHODS FOR REALIGNMENT
    9.
    发明申请
    RING OSCILLATOR, CONTROLLING CIRCUIT AND METHODS FOR REALIGNMENT 审中-公开

    公开(公告)号：US20200127648A1

    公开(公告)日：2020-04-23

    申请号：US16716910

    申请日：2019-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsien TSAI ,  Ruey-Bin SHEEN ,  Chih-Hsien CHANG ,  Cheng-Hsiang HSIEH

    IPC: H03K3/03

    Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.

    METHOD AND APPARATUS FOR PRECISION PHASE SKEW GENERATION
    10.
    发明申请
    METHOD AND APPARATUS FOR PRECISION PHASE SKEW GENERATION 审中-公开

    公开(公告)号：US20200099371A1

    公开(公告)日：2020-03-26

    申请号：US16436761

    申请日：2019-06-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mao-Hsuan CHOU ,  Ya-Tin CHANG ,  Ruey-Bin SHEEN ,  Chih-Hsien CHANG

    IPC: H03K5/14 ,  H03K5/135 ,  H03L7/089

    Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

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