公开(公告)号：US20190341543A1

公开(公告)日：2019-11-07

申请号：US16511862

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao LIAO ,  Chih-Wei LU ,  Hsi-Wen TIEN ,  Pin-Ren DAI ,  Chung-Ju LEE

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12

Abstract: A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.

公开(公告)号：US20190165256A1

公开(公告)日：2019-05-30

申请号：US15825972

申请日：2017-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen TIEN ,  Wei-Hao LIAO ,  Pin-Ren DAI ,  Chih-Wei LU ,  Chung-Ju LEE

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A method for forming a semiconductor device is provided. The method includes: providing a semiconductor substrate; forming a bottom electrode layer over the semiconductor substrate; forming a magnetic tunneling junction (MTJ) layer over the bottom electrode layer; forming a top electrode layer over the MTJ layer; and performing a single etch operation to etch the bottom electrode layer, the MTJ layer, and the top electrode layer, thereby forming a bottom electrode, a MTJ, and a top electrode respectively.

公开(公告)号：US20170140982A1

公开(公告)日：2017-05-18

申请号：US14942386

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen TIEN ,  Carlos H. DIAZ ,  Chung-Ju LEE ,  Shau-Lin SHUE ,  Tien-I BAO

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/311 ,  H01L21/288

CPC classification number: H01L21/7688 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2221/1063

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a sacrificial layer over the first dielectric layer. The method further includes forming an opening in the sacrificial layer and etching the first dielectric layer to form a via hole through the opening. The method further includes forming a conductive structure in the via hole and the opening and removing the sacrificial layer to expose an upper portion of the conductive structure. The method further includes forming a second dielectric layer around the upper portion of the conductive material.

公开(公告)号：US20240016064A1

公开(公告)日：2024-01-11

申请号：US18474173

申请日：2023-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen TIEN ,  Wei-Hao LIAO ,  Pin-Ren DAI ,  Chih-Wei LU ,  Chung-Ju LEE

IPC: H10N50/10 ,  G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01L23/5226 ,  H10B61/00 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A device includes a first dielectric layer, a magnetic tunnel junction (MTJ), an oxide layer, a cap layer, and a second dielectric layer. The MTJ is over the first dielectric layer. The oxide layer is over the first dielectric layer. The cap layer is over the first dielectric layer. The cap layer is in contact with a sidewall of the MTJ and a sidewall of the oxide layer. The second dielectric layer is over the cap layer.

公开(公告)号：US20220302376A1

公开(公告)日：2022-09-22

申请号：US17833688

申请日：2022-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao LIAO ,  Hsi-Wen TIEN ,  Chih-Wei LU ,  Pin-Ren DAI ,  Chung-Ju LEE

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: An integrated circuit includes a substrate, a bottom electrode, a dielectric layer, a metal-containing compound layer, a resistance switching element, and a top electrode. The bottom electrode is over the substrate, the bottom electrode having a bottom portion and a top portion over the bottom portion. The bottom portion of the bottom electrode has a sidewall slanted with respect to a sidewall of the top portion of the bottom electrode. The dielectric layer surrounds the bottom portion of the bottom electrode. The metal-containing compound layer surrounds the top portion of the bottom electrode. A top end of the sidewall of the bottom portion of the bottom electrode is higher than a bottom surface of the metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.

公开(公告)号：US20200373171A1

公开(公告)日：2020-11-26

申请号：US16988609

申请日：2020-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen TIEN ,  Wei-Hao LIAO ,  Chih-Wei LU ,  Pin-Ren DAI ,  Chung-Ju LEE

IPC: H01L21/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An interconnect structure includes a first dielectric layer, an etch stop layer, a conductive via, a conductive line, an intermediate conductive layer, a conductive pillar, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The conductive via is in the first dielectric layer and the etch stop layer. The conductive line is over the conductive via. The intermediate conductive layer is over the conductive line. The conductive pillar is over the intermediate conductive layer. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, and a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

公开(公告)号：US20200328343A1

公开(公告)日：2020-10-15

申请号：US16914296

申请日：2020-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao LIAO ,  Chih-Wei LU ,  Hsi-Wen TIEN ,  Pin-Ren DAI ,  Chung-Ju LEE

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A memory device includes a bottom electrode, an MTJ stack, and a top electrode. The bottom electrode has a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall. The MTJ stack is over the bottom electrode. The MTJ stack includes a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer. The bottom magnetic layer has a sidewall coterminous with the upper sidewall of the bottom electrode. The top magnetic layer has a sidewall laterally set back from the upper sidewall of the bottom electrode. The top electrode is over the MTJ stack.

公开(公告)号：US20190148633A1

公开(公告)日：2019-05-16

申请号：US16122179

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Ren DAI ,  Chung-Ju LEE ,  Chung-Te LIN ,  Chih-Wei LU ,  Hsi-Wen TIEN ,  Tai-Yen PENG ,  Chien-Min LEE ,  Wei-Hao LIAO

IPC: H01L43/12 ,  H01L27/22

Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

公开(公告)号：US20190067187A1

公开(公告)日：2019-02-28

申请号：US15689784

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Yung-Hsu WU ,  Chung-Ju LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The semiconductor device structure also includes a conductive via on the conductive line. The conductive via has an upper portion and a protruding portion. The protruding portion extends from a bottom of the upper portion towards the conductive line. The bottom of the upper portion is wider than a top of the upper portion. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the conductive line and the conductive via.

公开(公告)号：US20220271217A1

公开(公告)日：2022-08-25

申请号：US17740145

申请日：2022-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen TIEN ,  Wei-Hao LIAO ,  Pin-Ren DAI ,  Chih-Wei LU ,  Chung-Ju LEE

IPC: H01L43/08 ,  H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02 ,  H01L23/522

Abstract: A device includes a semiconductor substrate, a bottom conductive line, a bottom electrode, a magnetic tunneling junction (MTJ), and a residue. The bottom conductive line is over the semiconductor substrate. The bottom electrode is over the bottom conductive line. The MTJ is over the bottom electrode. The residue of the MTJ is on the sidewall of the bottom electrode and is spaced apart from the bottom conductive line.