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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210280434A1

    公开(公告)日：2021-09-09

    申请号：US17327580

    申请日：2021-05-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hsi-Wen TIEN ,  Wei-Hao LIAO ,  Chih-Wei LU ,  Pin-Ren DAI ,  Chung-Ju LEE

    IPC: H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

    Abstract: An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

    Magnetic Tunnel Junctions
    3.
    发明申请
    Magnetic Tunnel Junctions 审中-公开

    公开(公告)号：US20200235292A1

    公开(公告)日：2020-07-23

    申请号：US16840100

    申请日：2020-04-03

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Pin-Ren DAI ,  Chung-Ju LEE ,  Chung-Te LIN ,  Chih-Wei LU ,  Hsi-Wen TIEN ,  Tai-Yen PENG ,  Chien-Min LEE ,  Wei-Hao LIAO

    IPC: H01L43/12

    Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MU) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

    MEMORY DEVICE AND FABRICATION METHOD THEREOF
    4.
    发明申请
    MEMORY DEVICE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190341543A1

    公开(公告)日：2019-11-07

    申请号：US16511862

    申请日：2019-07-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Hao LIAO ,  Chih-Wei LU ,  Hsi-Wen TIEN ,  Pin-Ren DAI ,  Chung-Ju LEE

    IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12

    Abstract: A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190326157A1

    公开(公告)日：2019-10-24

    申请号：US16458399

    申请日：2019-07-01

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tai-I YANG ,  Wei-Chen CHU ,  Hsin-Ping CHEN ,  Chih-Wei LU ,  Chung-Ju LEE

    IPC: H01L21/768 ,  H01L23/528

    Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer, an etching stop layer, a barrier layer, a conductive layer, and a second dielectric layer. The first dielectric layer is over the integrated circuit. The etching stop layer is over the first dielectric layer. The barrier layer has an upper portion extending along a top surface of the etching stop layer and a lower portion extending downwardly from the upper portion along a sidewall of the etching stop layer and a sidewall of the first dielectric layer. The conductive layer is over the barrier layer and having a void region extending through the conductive layer, the barrier layer and the etching stop layer. The second dielectric layer is over the conductive layer and the void region.

    MEMORY DEVICE AND FABRICATION METHOD THEREOF
    9.
    发明申请
    MEMORY DEVICE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190165259A1

    公开(公告)日：2019-05-30

    申请号：US15860566

    申请日：2018-01-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Hao LIAO ,  Hsi-Wen TIEN ,  Chih-Wei LU ,  Pin-Ren DAI ,  Chung-Ju LEE

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

    Abstract: A method for fabricating a memory device includes forming a bottom electrode over a substrate; forming an etch stop layer over and surrounding the bottom electrode; removing at least one portion of the etch stop layer to expose the bottom electrode; forming a stack layer over the bottom electrode and a remaining portion of the etch stop layer, the stack layer comprising a resistance switching layer; and etching the stack layer to form a stack over the bottom electrode, the stack comprising a resistance switching element over the bottom electrode and a top electrode over the resistance switching element, wherein the etch stop layer has a higher etch resistance to the etching than that of the resistance switching element.

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