公开(公告)号：US09570539B2

公开(公告)日：2017-02-14

申请号：US14851357

申请日：2015-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/115

CPC classification number: H01L28/90 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/1157 ,  H01L27/11573 ,  H01L28/40 ,  H01L29/517 ,  H01L29/66545

Abstract: Some embodiments of the present disclosure relate to an integrated circuit (IC) arranged on a semiconductor substrate, which includes a flash region, a capacitor region, and a logic region. An upper substrate surface of the capacitor region is recessed relative to respective upper substrate surfaces of the flash and logic regions, respectively. A capacitor, which includes a polysilicon bottom electrode, a conductive top electrode arranged over the polysilicon bottom electrode, and a capacitor dielectric separating the bottom and top electrodes; is disposed over the recessed upper substrate surface of the capacitor region. A flash memory cell is disposed over the upper substrate surface of the flash region. The flash memory cell includes a select gate having a planarized upper surface that is co-planar with a planarized upper surface of the top electrode of the capacitor.

Abstract translation: 本公开的一些实施例涉及布置在半导体衬底上的集成电路（IC），其包括闪存区域，电容器区域和逻辑区域。 电容器区域的上基板表面分别相对于闪光和逻辑区域的相应上基板表面凹陷。 一种电容器，其包括多晶硅底部电极，布置在所述多晶硅底部电极上的导电顶部电极以及分离所述底部和顶部电极的电容器电介质; 设置在电容器区域的凹陷的上基板表面上。 闪存单元设置在闪光区域的上基板表面上。 闪存单元包括具有与电容器的顶部电极的平坦化上表面共面的平坦化上表面的选择栅极。

公开(公告)号：US11895836B2

公开(公告)日：2024-02-06

申请号：US17022390

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H10B41/10 ,  H10B41/50 ,  H01L29/423 ,  H01L29/51 ,  H01L21/033 ,  H01L21/321 ,  H01L21/308 ,  H01L21/28 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B41/50 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3212 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/518 ,  H10B41/10 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

公开(公告)号：US11195834B2

公开(公告)日：2021-12-07

申请号：US16866506

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L29/76 ,  H01L27/092 ,  H01L27/11546 ,  H01L27/11526 ,  H01L27/11575 ,  H01L29/10 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US11088040B2

公开(公告)日：2021-08-10

申请号：US16578303

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/423 ,  H01L27/11519

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US20200083126A1

公开(公告)日：2020-03-12

申请号：US16682210

申请日：2019-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/423

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US20190088561A1

公开(公告)日：2019-03-21

申请号：US15962177

申请日：2018-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529

CPC classification number: H01L22/34 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42328

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US10049939B2

公开(公告)日：2018-08-14

申请号：US15216569

申请日：2016-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.

公开(公告)号：US09831134B1

公开(公告)日：2017-11-28

申请号：US15278812

申请日：2016-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/266 ,  H01L21/762 ,  H01L21/761

CPC classification number: H01L21/823892 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0928

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US09679909B2

公开(公告)日：2017-06-13

申请号：US14750071

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC: H01L27/11 ,  H01L27/10 ,  H01L29/66 ,  H01L29/94 ,  H01L27/11575 ,  H01L27/1157

CPC classification number: H01L27/11575 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/945

Abstract: A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.

公开(公告)号：US20160379988A1

公开(公告)日：2016-12-29

申请号：US14750071

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC: H01L27/115

CPC classification number: H01L27/11575 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/945

Abstract: A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.

Abstract translation: 提供了一种用于形成分裂栅极闪存单元的方法，以及所得到的集成电路。 提供了具有存储单元和电容器区域的半导体衬底。 电容器区域包括一个或多个牺牲浅沟槽隔离（STI）区域。 执行第一蚀刻到一个或多个牺牲STI区域中以去除一个或多个牺牲STI区域并暴露对应于一个或多个牺牲STI区域的一个或多个沟槽。 将掺杂剂注入衬在一个或多个沟槽上的半导体衬底的区域中。 形成填充一个或多个沟槽的导电层。 执行第二蚀刻到导电层中以在存储单元区域上形成存储单元的控制栅极和选择栅极之一，并且在电容器区域上形成手指沟槽电容器的上部电极。