公开(公告)号：US10565345B2

公开(公告)日：2020-02-18

申请号：US16206881

申请日：2018-11-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Li-Chun Tien ,  Ting-Wei Chiang ,  Shun Li Chen ,  Ting Yu Chen ,  XinYong Wang

IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L27/02 ,  H01L27/118 ,  H01L23/522 ,  H01L23/528

摘要： A cell, in a semiconductor device, including: first and second active areas in a semiconductor substrate on opposite sides of the first axis; first, third and fifth, and correspondingly collinear second, fourth and sixth, having long axes in a second direction perpendicular to the first direction; the (A) first, third and fifth, and (B) second, fourth and sixth, conductive structures correspondingly overlapping the second active area; the first and second conductive structures correspondingly being centered between the (C) third and fifth, and (D) fourth and sixth, conductive structures; and a seventh conductive structure; the fourth conductive structure being located over first and second gaps between corresponding ones of the third through sixth, conductive structures; and the fourth conductive structure occupying an area which substantially overlaps one of the first and second conductive structures and a corresponding one of the first and second gaps.

公开(公告)号：US20200006217A1

公开(公告)日：2020-01-02

申请号：US16563215

申请日：2019-09-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung-Heng Hsieh ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Sheng-Hsiung Wang

IPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

摘要： A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

公开(公告)号：US20180337167A1

公开(公告)日：2018-11-22

申请号：US16051241

申请日：2018-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC分类号： H01L27/02 ,  H01L29/423 ,  G06F17/50 ,  H01L27/092 ,  H01L27/118

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  H01L27/092 ,  H01L29/42376 ,  H01L2027/11875

摘要： A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

公开(公告)号：US10127340B2

公开(公告)日：2018-11-13

申请号：US15370418

申请日：2016-12-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mao-Wei Chiu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Chi-Yu Lu

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L23/528

摘要： A method of designing, for a semiconductor device, a layout which includes standard spare cells. Such a method includes: generating a set of possible values for a first pitch of standard spare cells based on a second pitch of strap lines of a metallization layer; selecting one member of the possible values set to be the first pitch; and placing standard spare cells into a logic area of the layout according to the first pitch; wherein at least one of the generating, selecting and placing is executed by a processor of a computer.

公开(公告)号：US09899263B2

公开(公告)日：2018-02-20

申请号：US15150149

申请日：2016-05-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung-Heng Hsieh ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Min-Hsiung Chiang ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC分类号： G06F17/50 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/304 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/118

CPC分类号： H01L21/82345 ,  G06F17/5072 ,  H01L21/3043 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

公开(公告)号：US09831230B2

公开(公告)日：2017-11-28

申请号：US13965648

申请日：2013-08-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Li-Chun Tien ,  Ya-Chi Chou ,  Hui-Zhong Zhuang ,  Chun-Fu Chen ,  Ting-Wei Chiang ,  Hsiang Jen Tseng

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L27/11807 ,  H01L2027/11875

摘要： A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

公开(公告)号：US09501600B2

公开(公告)日：2016-11-22

申请号：US14051881

申请日：2013-10-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shang-Chih Hsieh ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng

IPC分类号： G06F17/50 ,  H03K19/02 ,  H01L27/02

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  H01L27/0207 ,  H03K19/02

摘要： An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.

摘要翻译： 通过具有金属线的标称最小间距的预定制造工艺制造集成电路。 集成电路包括沿着第一方向延伸的多条金属线和多条金属线下的多个标准单元。 多个金属线在与第一方向垂直的第二方向上以标称最小间距的整数倍分开。 多个标准单元包括被配置为执行预定功能并具有第一布局的第一标准单元和被配置为执行预定功能并且具有与第一布局不同的第二布局的第二标准单元。 第一和第二标准单元沿着第二方向具有单元高度（H），单元高度是标称最小间距的非整数倍。

公开(公告)号：US09412700B2

公开(公告)日：2016-08-09

申请号：US14515276

申请日：2014-10-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Ting-Wei Chiang ,  Sheng-Hsiung Wang ,  Li-Chun Tien

IPC分类号： H01L27/088 ,  H01L23/535 ,  H01L29/40 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

摘要翻译： 半导体器件包括具有有源区的衬底，衬底顶表面上的第一栅极结构，衬底顶表面上的第二栅极结构，第一栅极结构的每个侧壁上的一对第一间隔物， 在所述第二栅极结构的每个侧壁上的一对第二间隔物，至少所述第一栅极结构上的绝缘层，所述有源区上的第一导电特征和所述衬底上的第二导电特征。 此外，第二栅极结构与第一栅极结构相邻，并且第一导电特征的顶表面与第二导电特征的顶表面共面。

公开(公告)号：US09231106B2

公开(公告)日：2016-01-05

申请号：US13790814

申请日：2013-03-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Kuo-Nan Yang ,  Ming-Hsiang Song ,  Ta-Pen Guo

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/20 ,  H01L29/66

CPC分类号： H01L29/0847 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7835 ,  H01L29/785

摘要： Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.

摘要翻译： 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 实施例是一种半导体器件，包括在衬底上延伸的第一半导体鳍片，第一半导体鳍片上的第一源极区域和第一半导体鳍片上的第一漏极区域。 第一源区具有第一宽度，第一漏区具有第二宽度，第二宽度不同于第一宽度。

公开(公告)号：US09158877B2

公开(公告)日：2015-10-13

申请号：US14015924

申请日：2013-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shang-Chih Hsieh ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng

IPC分类号： G06F17/50 ,  H01L29/78

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/785

摘要： A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.

摘要翻译： 半导体结构包括第一有源区结构，围绕第一有源区结构的隔离结构，第一多晶硅结构，第一金属结构和第二金属结构。 第一个多晶硅结构超过了第一个有源区结构。 第一金属结构直接在第一有源区结构的第一部分之上。 第二金属结构直接与第一多晶硅结构的一部分接触并与第一金属结构接触。