公开(公告)号：US20210135093A1

公开(公告)日：2021-05-06

申请号：US17032638

申请日：2020-09-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.

公开(公告)号：US20250157501A1

公开(公告)日：2025-05-15

申请号：US18968522

申请日：2024-12-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Jui-Che Tsai ,  Perng-Fei Yuh ,  Yih Wang

IPC: G11C7/06 ,  H03K3/037 ,  H03K3/356 ,  H10D84/80

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

公开(公告)号：US12190986B2

公开(公告)日：2025-01-07

申请号：US18447904

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Jui-Che Tsai ,  Perng-Fei Yuh ,  Yih Wang

IPC: G11C7/06 ,  H01L27/06 ,  H03K3/037 ,  H03K3/356

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

公开(公告)号：US20240373625A1

公开(公告)日：2024-11-07

申请号：US18232580

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kao-Cheng Lin ,  Ku-Feng Lin ,  Preciliano Ruiz, Jr. ,  Chien-Ying Chen ,  Kazumasa Uno

IPC: H10B20/00

Abstract: A semiconductor device includes a memory array comprising a plurality of transistors arranged over a plurality of rows and a plurality of columns. The plurality of rows correspond to a plurality of active regions that continuously extend along a first lateral direction, respectively, and the plurality of columns correspond to a plurality of gate structures that discontinuously extend along a second lateral direction, respectively, the first lateral direction and the second lateral direction being perpendicular to each other. A first one of the gate structures comprising a first gap cutting the first gate structure and a second one of the gate structures comprising a second gap cutting the second gate structure are disposed immediately next to each other along the first lateral direction. The first gap and an extension of the second gap are offset from each other along the second lateral direction.

公开(公告)号：US20240312497A1

公开(公告)日：2024-09-19

申请号：US18677095

申请日：2024-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Ku-Feng Lin

IPC: G11C7/10 ,  G11C7/06 ,  G11C8/08

CPC classification number: G11C7/1012 ,  G11C7/06 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/1096 ,  G11C8/08

Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

公开(公告)号：US20240295603A1

公开(公告)日：2024-09-05

申请号：US18350512

申请日：2023-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-En Huang ,  Jui-Che Tsai ,  Ku-Feng Lin ,  Yih Wang

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  H03K19/173

CPC classification number: G01R31/3177 ,  G01R31/31725 ,  G01R31/318533 ,  H03K19/1737

Abstract: A circuit includes a plurality of first inputs corresponding to a first I/O of an I/O circuit and configured to receive at least a first input signal or a second input signal; a multiplexer compressor coupled to the plurality of first inputs, and configured to alternately form a first testing path for the first input signal and a second testing path for the second input signal; a first output configured to provide a first output signal, through one of the first testing path or the second testing path, as a shifted version of a third input signal; and a second output configured to provide a second output signal, through one of the first testing path or the second testing path, as a captured version of the first input signal or the second input signal.

公开(公告)号：US11961546B2

公开(公告)日：2024-04-16

申请号：US17391639

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Po-Hao Lee ,  Ku-Feng Lin ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/06 ,  G11C11/08 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  H10B61/22 ,  H10N50/10

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

公开(公告)号：US20230298665A1

公开(公告)日：2023-09-21

申请号：US18300706

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Ku-Feng Lin ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Fu-An Wu

IPC: G11C14/00 ,  G11C11/419 ,  G11C11/16

CPC classification number: G11C14/0081 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/419

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

公开(公告)号：US20230206963A1

公开(公告)日：2023-06-29

申请号：US18177749

申请日：2023-03-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C7/06

CPC classification number: G11C7/062

Abstract: A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.

公开(公告)号：US11688436B2

公开(公告)日：2023-06-27

申请号：US17829333

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.