公开(公告)号：US10291212B2

公开(公告)日：2019-05-14

申请号：US15969437

申请日：2018-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Su Kim ,  Dae Seong Lee

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/20

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

公开(公告)号：US09345114B2

公开(公告)日：2016-05-17

申请号：US14460313

申请日：2014-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Seob Kim ,  Min Su Kim

IPC: H05B37/02 ,  H05B33/08

CPC classification number: H05B33/0872 ,  H05B33/0854 ,  H05B37/0218 ,  H05B37/0254 ,  H05B37/0272

Abstract: A lighting system includes a digital addressable lighting interface (DALI) master controller, a lighting driver, and a signal converter. The DALI master controller is connected to a management server. The lighting driver operates a lighting device including a light emitting diode (LED). The signal converter is connected to the DALI master controller by a DALI bus operating according to a DALI communication protocol, and is communicatively connected to the lighting driver via a wireless communication connection operating according to a wireless communication protocol. The signal converter inter-converts a signal transmitted and received from the DALI master controller according to the DALI communication protocol and a signal transmitted to and received from the lighting driver according to the wireless communication protocol so as to enable communication between the lighting driver and the DALI master controller.

Abstract translation: 照明系统包括数字可寻址照明接口（DALI）主控制器，照明驱动器和信号转换器。 DALI主控制器连接到管理服务器。 照明驱动器操作包括发光二极管（LED）的照明装置。 信号转换器通过根据DALI通信协议操作的DALI总线连接到DALI主控制器，并且通过根据无线通信协议操作的无线通信连接通信地连接到照明驱动器。 信号转换器根据DALI通信协议将从DALI主控制器发送和接收的信号和根据无线通信协议发送到照明驱动器的信号和从照明驱动器接收的信号相互转换，以使得照明驱动器和 DALI主控制器。

公开(公告)号：US08928354B2

公开(公告)日：2015-01-06

申请号：US13725208

申请日：2012-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Su Kim

IPC: H03K19/096

CPC classification number: H03K19/0963 ,  H03K19/096 ,  H03K19/0966

Abstract: A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.

Abstract translation: 时钟延迟的多米诺骨牌逻辑电路包括预充电电路，其被配置为响应于时钟信号来控制第一节点和动态节点之间的连接，评估电路被配置为响应于时钟来控制第二节点和评估节点之间的连接 信号，连接在所述动态节点和所述评估节点之间的逻辑网络，所述逻辑网络被配置为基于多个输入信号来确定所述动态节点的逻辑电平;以及相位控制电路，被配置为输出所述评估的逻辑电平 节点或第一节点的逻辑电平。

公开(公告)号：US12272694B2

公开(公告)日：2025-04-08

申请号：US17680907

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Seong Lee ,  Ah Reum Kim ,  Min Su Kim

IPC: H01L27/118

Abstract: A semiconductor device includes first, second, and third power rails extending in a first direction on a substrate and sequentially spaced apart in a second direction intersecting the first direction. A fourth power rail extends in the first direction on the substrate between the first and third power rails. A first well of a first conductive type is displaced inside the substrate between the first and third power rails. Cells are continuously displaced between the first and third power rails and share the first well. The first and third power rails are provided with a first voltage, the second power rail is provided with a second voltage different from the first voltage, the fourth power rail is provided with a third voltage different from the first voltage and the second voltage, and the cells are provided with the third voltage from the fourth power rail.

公开(公告)号：US11799458B2

公开(公告)日：2023-10-24

申请号：US17693026

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young O Lee ,  Min Su Kim ,  Jeong Jin Lee ,  Won Hyun Choi

IPC: H03K3/012 ,  H03K3/037 ,  H03K3/017

CPC classification number: H03K3/0375 ,  H03K3/012 ,  H03K3/017

Abstract: A pulse-based flip flop circuit includes a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving either a data signal or the scan input signal responsive to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes a direct path providing a clock signal as a direct path input to a NAND circuit; a delay path including a number of plural stages that delay the clock signal and provide a delayed clock signal as a delay path input to the NAND circuit that performs a NAND operation on the direct path and delay path inputs to generate the inverted pulse signal; and a feedback path providing the pulse signal to a first stage among the stages of the delay path.

公开(公告)号：US11386254B2

公开(公告)日：2022-07-12

申请号：US16549989

申请日：2019-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah Reum Kim ,  Min Su Kim ,  Young O Lee

IPC: G06F30/398 ,  H01L27/092 ,  H01L27/02 ,  G06F30/392

Abstract: A semiconductor circuit and a layout system of the semiconductor circuit, the semiconductor circuit including a latch; a feedback inverter that receives an output signal of the latch via a first node and provides a feedback signal to the latch responsive to the output signal of the latch; and an output driver which receives the output signal of the latch via the first node and provides an output signal externally of the semiconductor circuit. The output driver includes an even number of inverters, and the latch, the feedback inverter, and the output driver share a single active region formed without isolation.

公开(公告)号：US11302694B2

公开(公告)日：2022-04-12

申请号：US16733634

申请日：2020-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Seong Lee ,  Min Su Kim

IPC: H01L27/092 ,  H03K19/20 ,  H01L23/528 ,  H03K19/0948 ,  H03K3/356 ,  H03K3/3562 ,  H01L27/02 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

公开(公告)号：US20210373996A1

公开(公告)日：2021-12-02

申请号：US17177415

申请日：2021-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok Ho Seo ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Min Su Kim ,  Won Jae Shin ,  Yong Jun Yu ,  Chang Min Lee ,  Il Gyu Jung ,  In Su Choi

IPC: G06F11/10 ,  G11C11/406

Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.

公开(公告)号：US10608615B2

公开(公告)日：2020-03-31

申请号：US15417339

申请日：2017-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Woo Kim ,  Ju Hyun Kang ,  Min Su Kim ,  Ka Ram Lee

IPC: H03K3/012 ,  H03K3/3562

Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.

公开(公告)号：US10523188B2

公开(公告)日：2019-12-31

申请号：US15427444

申请日：2017-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Kyum Kim ,  Dae Seong Lee ,  Min Su Kim

IPC: H03K3/00 ,  H03K3/356 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L27/105

Abstract: A semiconductor device includes: first through fourth active regions spaced apart from one another; a first gate line disposed to overlap with the first and second active regions, but not with the third and fourth active regions, and to extend in a first direction; a second gate line disposed to overlap with the third and fourth active regions, but not with the first and second active regions, and to extend in the first direction while being spaced apart from the first gate line; and a dummy gate line disposed to overlap with the first through fourth active regions and a field region, to be spaced apart from the first and second gate lines in a second direction, and to extend in the first direction, wherein a signal input to the first or second active region is transmitted to the third or fourth active region.