公开(公告)号：US10673420B2

公开(公告)日：2020-06-02

申请号：US15981415

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Lee ,  Dae Seong Lee ,  Minsu Kim ,  Ahreum Kim ,  Chunghee Kim

IPC: H03K3/037 ,  H03K19/20 ,  G06F1/10 ,  G01R31/317 ,  G01R31/3177

Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.

公开(公告)号：US10587249B2

公开(公告)日：2020-03-10

申请号：US16411562

申请日：2019-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Su Kim ,  Dae Seong Lee

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/20

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

公开(公告)号：US10291212B2

公开(公告)日：2019-05-14

申请号：US15969437

申请日：2018-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Su Kim ,  Dae Seong Lee

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/20

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

公开(公告)号：US11842999B2

公开(公告)日：2023-12-12

申请号：US17666872

申请日：2022-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Seong Lee ,  Min Su Kim

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/02 ,  H01L29/78 ,  H03K3/356 ,  H03K3/3562 ,  H03K19/0948 ,  H03K19/20 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/785 ,  H03K3/35625 ,  H03K3/356156 ,  H03K19/0948 ,  H03K19/20 ,  H01L21/823828 ,  H01L21/823871

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

公开(公告)号：US10062697B2

公开(公告)日：2018-08-28

申请号：US15428308

申请日：2017-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Seong Lee ,  Min Su Kim

IPC: H01L21/70 ,  H01L27/092 ,  H03K19/20 ,  H01L23/528 ,  H03K19/0948 ,  H01L29/78 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H01L27/0924 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/785 ,  H03K3/356156 ,  H03K3/35625 ,  H03K19/0948 ,  H03K19/20

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

公开(公告)号：US10553585B2

公开(公告)日：2020-02-04

申请号：US16059562

申请日：2018-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Seong Lee ,  Min Su Kim

IPC: H01L27/092 ,  H03K19/20 ,  H01L23/528 ,  H03K19/0948 ,  H03K3/356 ,  H03K3/3562 ,  H01L27/02 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

公开(公告)号：US20190267974A1

公开(公告)日：2019-08-29

申请号：US16411562

申请日：2019-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MIN SU KIM ,  Dae Seong Lee

IPC: H03K3/3562

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

公开(公告)号：US12272694B2

公开(公告)日：2025-04-08

申请号：US17680907

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Seong Lee ,  Ah Reum Kim ,  Min Su Kim

IPC: H01L27/118

Abstract: A semiconductor device includes first, second, and third power rails extending in a first direction on a substrate and sequentially spaced apart in a second direction intersecting the first direction. A fourth power rail extends in the first direction on the substrate between the first and third power rails. A first well of a first conductive type is displaced inside the substrate between the first and third power rails. Cells are continuously displaced between the first and third power rails and share the first well. The first and third power rails are provided with a first voltage, the second power rail is provided with a second voltage different from the first voltage, the fourth power rail is provided with a third voltage different from the first voltage and the second voltage, and the cells are provided with the third voltage from the fourth power rail.

公开(公告)号：US11302694B2

公开(公告)日：2022-04-12

申请号：US16733634

申请日：2020-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Seong Lee ,  Min Su Kim

IPC: H01L27/092 ,  H03K19/20 ,  H01L23/528 ,  H03K19/0948 ,  H03K3/356 ,  H03K3/3562 ,  H01L27/02 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

公开(公告)号：US10523188B2

公开(公告)日：2019-12-31

申请号：US15427444

申请日：2017-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Kyum Kim ,  Dae Seong Lee ,  Min Su Kim

IPC: H03K3/00 ,  H03K3/356 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L27/105

Abstract: A semiconductor device includes: first through fourth active regions spaced apart from one another; a first gate line disposed to overlap with the first and second active regions, but not with the third and fourth active regions, and to extend in a first direction; a second gate line disposed to overlap with the third and fourth active regions, but not with the first and second active regions, and to extend in the first direction while being spaced apart from the first gate line; and a dummy gate line disposed to overlap with the first through fourth active regions and a field region, to be spaced apart from the first and second gate lines in a second direction, and to extend in the first direction, wherein a signal input to the first or second active region is transmitted to the third or fourth active region.