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公开(公告)号：US20220375963A1
公开(公告)日：2022-11-24
申请号：US17680907
申请日：2022-02-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： DAE SEONG LEE , AH REUM KIM , MIN SU KIM
IPC: H01L27/118
Abstract: A semiconductor device includes first, second, and third power rails extending in a first direction on a substrate and sequentially spaced apart in a second direction intersecting the first direction. A fourth power rail extends in the first direction on the substrate between the first and third power rails. A first well of a first conductive type is displaced inside the substrate between the first and third power rails. Cells are continuously displaced between the first and third power rails and share the first well. The first and third power rails are provided with a first voltage, the second power rail is provided with a second voltage different from the first voltage, the fourth power rail is provided with a third voltage different from the first voltage and the second voltage, and the cells are provided with the third voltage from the fourth power rail.
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公开(公告)号：US20220393671A1
公开(公告)日：2022-12-08
申请号：US17693026
申请日：2022-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YOUNG O LEE , MIN SU KIM , JEONG JIN LEE , WON HYUN CHOI
Abstract: A pulse-based flip flop circuit includes; a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving one of a data signal and the scan input signal in response to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes; a direct path providing a clock signal as a direct path input to a NAND circuit, a delay path including a number of stages configured to delay the clock signal and provide a delayed clock signal as a delay path input to NAND circuit, wherein the NAND circuit performs a NAND operation on the direct path input and the delay path input to generate the inverted pulse signal, and a feedback path providing the pulse signal to a first stage among the number of stages of the delay path.
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公开(公告)号：US20190052249A1
公开(公告)日：2019-02-14
申请号：US16164329
申请日：2018-10-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： MIN SU KIM
Abstract: A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.
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Patent Agency Ranking
公开(公告)号：US20170317676A1
公开(公告)日：2017-11-02
申请号：US15499257
申请日：2017-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： AH REUM KIM , MIN SU KIM , CHUNG HEE KIM , HYUN CHUL HWANG
IPC: H03K19/00 , H03K19/20 , H03K19/003
CPC classification number: H03K19/0013 , H03K3/012 , H03K3/356026 , H03K19/00315 , H03K19/20
Abstract: A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.
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5.发明申请公开(公告)号：US20170237414A1
公开(公告)日：2017-08-17
申请号：US15586011
申请日：2017-05-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： MIN SU KIM , JONG WOO KIM , JI KYUM KIM
IPC: H03K3/012 , H03K19/00 , H03K3/3562
CPC classification number: H03K3/012 , H03K3/0372 , H03K3/35625 , H03K19/0002
Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.
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公开(公告)号：US20170063349A1
公开(公告)日：2017-03-02
申请号：US15245239
申请日：2016-08-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： MIN SU KIM
Abstract: A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.
Abstract translation: 半导体电路包括接收第一输入信号，时钟信号和反馈信号的输入的第一逻辑门，并执行第一逻辑运算以输出第一输出信号。 第二逻辑门，其接收第一逻辑门的第一输出信号，时钟信号和第一输入信号的反相输出信号的输入，并执行第二逻辑运算以输出反馈信号。
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公开(公告)号：US20220085797A1
公开(公告)日：2022-03-17
申请号：US17449079
申请日：2021-09-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SAN HA KIM , TAEK KYUN SHIN , MIN SU KIM
IPC: H03K3/037 , G01R31/3183 , H03K19/20
Abstract: A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.
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公开(公告)号：US20190267974A1
公开(公告)日：2019-08-29
申请号：US16411562
申请日：2019-05-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： MIN SU KIM , Dae Seong Lee
IPC: H03K3/3562
Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.
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