公开(公告)号：US10608615B2

公开(公告)日：2020-03-31

申请号：US15417339

申请日：2017-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Woo Kim ,  Ju Hyun Kang ,  Min Su Kim ,  Ka Ram Lee

IPC: H03K3/012 ,  H03K3/3562

Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.

公开(公告)号：US10404240B2

公开(公告)日：2019-09-03

申请号：US15399146

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Woo Kim ,  Min Su Kim ,  Ah Reum Kim ,  Chung Hee Kim

IPC: H03K3/356 ,  H03K3/3562 ,  H03K3/037

Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.

公开(公告)号：US10333498B2

公开(公告)日：2019-06-25

申请号：US15586011

申请日：2017-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Su Kim ,  Jong Woo Kim ,  Ji Kyum Kim

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037 ,  H03K3/3562 ,  H03K19/00

Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.