公开(公告)号：US09876500B2

公开(公告)日：2018-01-23

申请号：US15499257

申请日：2017-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah Reum Kim ,  Min Su Kim ,  Chung Hee Kim ,  Hyun Chul Hwang

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/20

CPC classification number: H03K19/0013 ,  H03K3/012 ,  H03K3/356026 ,  H03K19/00315 ,  H03K19/20

Abstract: A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.

公开(公告)号：US12272694B2

公开(公告)日：2025-04-08

申请号：US17680907

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Seong Lee ,  Ah Reum Kim ,  Min Su Kim

IPC: H01L27/118

Abstract: A semiconductor device includes first, second, and third power rails extending in a first direction on a substrate and sequentially spaced apart in a second direction intersecting the first direction. A fourth power rail extends in the first direction on the substrate between the first and third power rails. A first well of a first conductive type is displaced inside the substrate between the first and third power rails. Cells are continuously displaced between the first and third power rails and share the first well. The first and third power rails are provided with a first voltage, the second power rail is provided with a second voltage different from the first voltage, the fourth power rail is provided with a third voltage different from the first voltage and the second voltage, and the cells are provided with the third voltage from the fourth power rail.

公开(公告)号：US11386254B2

公开(公告)日：2022-07-12

申请号：US16549989

申请日：2019-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah Reum Kim ,  Min Su Kim ,  Young O Lee

IPC: G06F30/398 ,  H01L27/092 ,  H01L27/02 ,  G06F30/392

Abstract: A semiconductor circuit and a layout system of the semiconductor circuit, the semiconductor circuit including a latch; a feedback inverter that receives an output signal of the latch via a first node and provides a feedback signal to the latch responsive to the output signal of the latch; and an output driver which receives the output signal of the latch via the first node and provides an output signal externally of the semiconductor circuit. The output driver includes an even number of inverters, and the latch, the feedback inverter, and the output driver share a single active region formed without isolation.

公开(公告)号：US10404240B2

公开(公告)日：2019-09-03

申请号：US15399146

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Woo Kim ,  Min Su Kim ,  Ah Reum Kim ,  Chung Hee Kim

IPC: H03K3/356 ,  H03K3/3562 ,  H03K3/037

Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.