Invention Grant
- Patent Title: Master-slave flip flop
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Application No.: US15969437Application Date: 2018-05-02
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Publication No.: US10291212B2Publication Date: 2019-05-14
- Inventor: Min Su Kim , Dae Seong Lee
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2017-0120662 20170919
- Main IPC: H03K3/356
- IPC: H03K3/356 ; H03K3/3562 ; H03K19/20

Abstract:
A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.
Public/Granted literature
- US20190089338A1 MASTER-SLAVE FLIP FLOP Public/Granted day:2019-03-21
Information query
IPC分类: