公开(公告)号：US20160225621A1

公开(公告)日：2016-08-04

申请号：US15097369

申请日：2016-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： YuJeong SEO ,  JinTaek PARK ,  Youngwoo PARK

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/04 ,  H01L29/16 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L21/02672 ,  H01L21/02532 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 根据该方法，重复堆叠具有预定高度和有效孔的子堆叠结构。 因此，可以改善电池分散，并且可以防止在蚀刻工艺中引起的各种误差，例如不开放的误差。 作为通道使用的活性柱的粒径可以使用金属诱导横向结晶法增加或最大化，从而可提高电池电流。 可以控制包括结晶诱导金属的金属硅化物层的形成位置，使得可以根据活性柱中的位置来控制结晶诱导金属的浓度等级。

公开(公告)号：US20240061637A1

公开(公告)日：2024-02-22

申请号：US18350277

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjun PARK ,  Seungeon KIM ,  Youngwoo PARK

IPC: G06F3/14 ,  G06F3/0482 ,  G06F3/04845

CPC classification number: G06F3/1454 ,  G06F3/0482 ,  G06F3/04845 ,  G06F2203/04803

Abstract: A display device may include: a display, a communication interface comprising circuitry configured to transmit and/or receive data to and from a plurality of electronic devices, a memory storing one or more instructions, and at least one processor configured to execute the one or more instructions to: split a screen of the display device into a plurality of regions and obtain pieces of display information respectively corresponding to the plurality of regions, control the communication interface to transmit first display information corresponding to a first region among the plurality of regions to a first electronic device corresponding to the first region among the plurality of electronic devices, receive, from the first electronic device, a first image obtained based on the first display information, and control the display to display the first image in the first region.

公开(公告)号：US20170186758A1

公开(公告)日：2017-06-29

申请号：US15458273

申请日：2017-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun LEE ,  Dohyun LEE ,  Youngwoo PARK ,  Su Jin AHN ,  Jaeduk LEE

IPC: H01L27/11524 ,  G11C16/34 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/1157

CPC classification number: H01L27/11524 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16

Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.

公开(公告)号：US20240419932A1

公开(公告)日：2024-12-19

申请号：US18739968

申请日：2024-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwoo PARK

IPC: G06K19/077 ,  G06F13/38

Abstract: A storage device includes a storage controller and a printed circuit board. The printed circuit board includes a host interface connector including first pins coupled to an external host device, a controller socket in which the storage controller is mounted, and a first slot that may receive a first secure digital (SD) Express device, the first slot including second pins to be coupled to the first SD Express device. A first receive pin among the first pins is connected to a first receive pin among the second pins, a second receive pin among the first pins is connected to a second receive pin among the second pins, a first transmit pin among the first pins is connected to a first transmit pin among the second pins, and a second transmit pin among the first pins is connected to a second transmit pin among the second pins.

公开(公告)号：US20200161179A1

公开(公告)日：2020-05-21

申请号：US16751744

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun LEE ,  Youngwoo PARK ,  Junghoon PARK ,  Jaeduk LEE

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US20170287930A1

公开(公告)日：2017-10-05

申请号：US15593494

申请日：2017-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun LEE ,  Heonkyu LEE ,  Shinhwan KANG ,  Youngwoo PARK

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.

公开(公告)号：US20140231899A1

公开(公告)日：2014-08-21

申请号：US14265959

申请日：2014-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo LEE ,  Byungkwan YOU ,  Youngwoo PARK ,  Kwang Soo SEOL

IPC: H01L27/115

CPC classification number: H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

Abstract: Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

Abstract translation: 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。