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11.发明授权Resistive memory device, resistive memory system and method of operating the resistive memory device 有权电阻式存储器件，电阻式存储器系统和操作电阻式存储器件的方法公开(公告)号：US09449686B2
公开(公告)日：2016-09-20
申请号：US14743488
申请日：2015-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon
CPC classification number: G11C13/004 , G11C11/1655 , G11C11/1657 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069
Abstract: A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address.
Abstract translation: 一种操作电阻式存储器件和包括电阻性存储器件的电阻式存储器系统的方法是用于包括多个位线和至少一个虚拟位线的电阻式存储器件。 操作电阻式存储器件的方法包括检测伴随第一命令的第一地址，产生用于偏置非选择线路的多个禁止电压，以及向第一伪位线提供从多个禁止中选择的第一禁止电压 基于检测到第一地址的结果的电压。
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公开(公告)号：US09384832B2
公开(公告)日：2016-07-05
申请号：US14791636
申请日：2015-07-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C11/1673 , G11C11/56 , G11C13/0004 , G11C13/0007 , G11C2213/72
Abstract: A method is for operating a memory device including a plurality of memory cells disposed in regions where a plurality of first signal lines and a plurality of second signal lines cross each other. The method includes applying an initial voltage to the plurality of first signal lines, floating the plurality of first signal lines to which the initial voltage is applied, applying a second inhibit voltage to the plurality of second signal lines, and increasing voltage levels of the plurality of first signal lines to a first inhibit voltage level via capacitive coupling between the plurality of first signal lines which are floated and the plurality of second signal lines to which the second inhibit voltage is applied.
Abstract translation: 一种用于操作存储器件的方法，该存储器件包括设置在多个第一信号线和多条第二信号线彼此交叉的区域中的多个存储单元。 该方法包括将初始电压施加到多个第一信号线，使施加有初始电压的多条第一信号线浮置，向多条第二信号线施加第二禁止电压，以及增加多个第一信号线的电压电平 的第一信号线通过在浮置的多个第一信号线之间的电容耦合和施加第二禁止电压的多个第二信号线之间的第一禁止电压电平。
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13.发明授权Nonvolatile memory device using variable resistance material and method for driving the same 有权使用可变电阻材料的非易失性存储器件及其驱动方法公开(公告)号：US09196358B2
公开(公告)日：2015-11-24
申请号：US13963417
申请日：2013-08-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung Yeon Lee , Yeong-Taek Lee
CPC classification number: G11C13/004 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0061 , G11C2213/71 , G11C2213/72
Abstract: The nonvolatile memory device using a variable resistance material and a method for driving the same are provided. A first clamping unit connected between a resistance memory cell and a first sensing node to provide a first clamping bias to the resistance memory cell. The first clamping bias changes over time. A first compensation unit provides a compensation current to the first sensing node. A first sense amplifier is connected to the first sensing node to sense a level change of the first sensing node. In response to if first data stored in the resistance memory cell, an output value of the first sense amplifier transitions to a different state after a first amount of time from a time point from where the first clamping bias starts. In response to second data that is different from the first data stored in the resistance memory cell, the output value of the first sense amplifier transitions to the different state after a second amount of time that is different from the first amount of time from the time point from where the first clamping bias starts.
Abstract translation: 提供了使用可变电阻材料的非易失性存储器件及其驱动方法。 连接在电阻存储单元和第一感测节点之间的第一钳位单元，用于向电阻存储单元提供第一钳位偏置。 第一个钳位偏置随时间而变化。 第一补偿单元向第一感测节点提供补偿电流。 第一读出放大器连接到第一感测节点以感测第一感测节点的电平变化。 响应于如果存储在电阻存储器单元中的第一数据，则第一读出放大器的输出值在从第一钳位偏置开始的时间点开始的第一时间量之后转变到不同的状态。 响应于与存储在电阻存储器单元中的第一数据不同的第二数据，第一读出放大器的输出值在从与时间不同的第一时间量的第二时间量之后转变到不同状态 从第一个夹紧偏置开始的点。
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14.发明申请NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTANCE MATERIAL AND METHOD FOR DRIVING THE SAME 有权使用可变电阻材料的非易失性存储器件及其驱动方法公开(公告)号：US20140119095A1
公开(公告)日：2014-05-01
申请号：US13963417
申请日：2013-08-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung Yeon Lee , Yeong-Taek Lee
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0061 , G11C2213/71 , G11C2213/72
Abstract: The nonvolatile memory device using a variable resistance material and a method for driving the same are provided. A first clamping unit connected between a resistance memory cell and a first sensing node to provide a first clamping bias to the resistance memory cell. The first clamping bias changes over time. A first compensation unit provides a compensation current to the first sensing node. A first sense amplifier is connected to the first sensing node to sense a level change of the first sensing node. In response to if first data stored in the resistance memory cell, an output value of the first sense amplifier transitions to a different state after a first amount of time from a time point from where the first clamping bias starts. In response to second data that is different from the first data stored in the resistance memory cell, the output value of the first sense amplifier transitions to the different state after a second amount of time that is different from the first amount of time from the time point from where the first clamping bias starts.
Abstract translation: 提供了使用可变电阻材料的非易失性存储器件及其驱动方法。 连接在电阻存储单元和第一感测节点之间的第一钳位单元，用于向电阻存储单元提供第一钳位偏置。 第一个钳位偏置随时间而变化。 第一补偿单元向第一感测节点提供补偿电流。 第一读出放大器连接到第一感测节点以感测第一感测节点的电平变化。 响应于如果存储在电阻存储器单元中的第一数据，则第一读出放大器的输出值在从第一钳位偏置开始的时间点开始的第一时间量之后转变到不同的状态。 响应于与存储在电阻存储器单元中的第一数据不同的第二数据，第一读出放大器的输出值在从与时间不同的第一时间量的第二时间量之后转变到不同状态 从第一个夹紧偏置开始的点。
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公开(公告)号：US09613697B2
公开(公告)日：2017-04-04
申请号：US15151661
申请日：2016-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon
CPC classification number: G11C13/0069 , G11C11/56 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2013/0078 , G11C2213/15 , G11C2213/71 , G11C2213/72 , G11C2213/79
Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells respectively connected to a plurality of first signal lines and a plurality of second signal lines crossing each other. A first write driver is configured to provide a write voltage to write data to the memory cells. A second write driver is configured to be disposed between the memory cell array and the first write driver and provide a write current generated based on the write voltage to a first signal line selected from among the plurality of first signal lines.
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Patent Agency Ranking
16.发明授权Resistive memory device having memory cell arrays with multiple stack layers and bad-region managing circuit and method for managing short failure 有权具有具有多个堆叠层的存储单元阵列和不良区域管理电路的电阻式存储器件以及用于管理短路故障的方法公开(公告)号：US09570200B2
公开(公告)日：2017-02-14
申请号：US14743521
申请日：2015-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Yong-Kyu Lee , Hyun-Kook Park
CPC classification number: G11C29/76 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C13/0002 , G11C13/0023 , G11C13/0059 , G11C13/0064 , G11C13/0069 , G11C29/808 , G11C2029/4402 , G11C2213/71
Abstract: A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
Abstract translation: 电阻式存储器件包括存储单元阵列，其包括沿垂直方向堆叠的多个存储层。 多个存储层中的每一个包括设置在多个第一线和多条第二线彼此交叉的区域中的多个存储单元。 不良区域管理单元将包括来自多个存储器单元中的不良单元和至少一个第二存储器层的第一存储器层定义为不良区域。
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公开(公告)号：US09472282B2
公开(公告)日：2016-10-18
申请号：US14979947
申请日：2015-12-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Yeong-Taek Lee , Dae-Seok Byeon , Chi-Weon Yoon
CPC classification number: G11C13/0069 , G11C5/063 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0064 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
Abstract: A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.
Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列具有分别布置在多个第一信号线和多个第二信号线彼此交叉的区域上的多个电阻存储单元。 写入电路连接到从多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线，并向所选存储单元提供脉冲。 电压检测器检测所选择的第一信号线和写入电路之间的连接节点处的节点电压。 电压产生电路产生分别施加到从多个存储单元中连接到未选择的存储单元的未选择的第一和第二信号线的第一禁止电压和第二禁止电压，并且基于 检测到的节点电压。
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18.发明授权Resistive memory device and method of operating the same to reduce leakage current 有权电阻式存储器件及其操作方法，以减少漏电流公开(公告)号：US09361974B2
公开(公告)日：2016-06-07
申请号：US14683269
申请日：2015-04-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Hyun-Kook Park , Hyo-Jin Kwon
CPC classification number: G11C13/0023 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0078
Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.
Abstract translation: 一种操作存储器件的方法包括从多个第一信号线中确定流过所选择的第一信号线的工作电流的值，所述第一信号线被施加选择电压; 将存储单元阵列划分为n个块，n是大于1的整数，基于工作电流的值; 以及将对应于n个块的具有不同电压电平的抑制电压施加到包括在n个块中的未选择的第二信号线。 每个未选择的第二信号线是由于流过所选择的第一信号线的工作电流和由未选择的第二信号线和所选择的第一信号线寻址的存储器单元而引起的漏电流可能流过的通路。
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19.发明授权Resistive memory device, resistive memory system, and method of operating resistive memory device 有权电阻式存储器件，电阻式存储器系统和操作电阻式存储器件的方法公开(公告)号：US09269429B2
公开(公告)日：2016-02-23
申请号：US14665127
申请日：2015-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Dae-Seok Byeon , Yeong-Taek Lee , Bo-Geun Kim , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C5/025 , G11C13/0023 , G11C13/0033 , G11C2213/71
Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.
Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列包括多个垂直层叠的层，其中一层被指定为无干扰层，另一层指定为禁止访问层，其中无干扰层和禁止访问层共享与 禁止至少一条信号线和针对存储器单元访问禁止层的访问操作。
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20.发明申请NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT AND MEMORY SYSTEM HAVING THE SAME 有权使用可变电阻元件的非易失性存储器件及其相关的存储器系统公开(公告)号：US20140198556A1
公开(公告)日：2014-07-17
申请号：US14099330
申请日：2013-12-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Yeon Lee , Yeong-Taek Lee
IPC: G11C7/06
CPC classification number: G11C7/14 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C11/406 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C16/28 , G11C16/3418 , G11C2013/0054 , G11C2213/71 , G11C2213/72
Abstract: A nonvolatile memory device, which has an improved read reliability through a refresh operation, and a memory system, are provided. The nonvolatile memory device includes a resistive memory cell, a reference resistor corresponding to the resistive memory cell, a reference sense amplifier electrically connected to the reference resistor and configured to change a transition time of an output value of the reference resistor, and a refresh request signal generator configured to output the refresh request signal for the resistive memory cell when the transition time of an output value of the reference resistor is in a preset refresh requiring period.
Abstract translation: 提供了通过刷新操作具有改善的读取可靠性的非易失性存储器件和存储器系统。 非易失性存储器件包括电阻存储单元，对应于电阻存储单元的参考电阻，与参考电阻器电连接并被配置为改变参考电阻器的输出值的转换时间的参考读出放大器和刷新请求 信号发生器被配置为当参考电阻器的输出值的转换时间处于预设的刷新需求周期时，输出用于电阻性存储器单元的刷新请求信号。
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