知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

30 records (took 0.019 seconds)

    SEMICONDUCTOR DEVICE
    12.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240312903A1

    公开(公告)日：2024-09-19

    申请号：US18599910

    申请日：2024-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangkoo Kang ,  Wookyung You ,  Koungmin Ryu ,  Hoonseok Seo ,  Woojin Lee

    IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/78696

    Abstract: Provided is a semiconductor device, the semiconductor device, including: a plurality of fin-type active patterns extending in a first direction on a substrate; a gate structure extending in a second direction, and crossing the plurality of fin-type active patterns; a plurality of separation structures extending in the second direction; source/drain regions disposed on the plurality of fin-type active patterns on both sides of the gate structure; an interlayer insulating layer covering the source/drain regions on the substrate; a contact structure connected to at least one of the source/drain regions; a buried conductive structure electrically connected to the contact structure in the interlayer insulating layer, and having a first width defined by a distance between adjacent separation structures among the plurality of separation structures; and a power transmission structure extending from the second surface toward the first surface of the substrate, and connected to the buried conductive structure.

    Semiconductor devices
    14.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11721622B2

    公开(公告)日：2023-08-08

    申请号：US17453197

    申请日：2021-11-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoo Shin ,  Sanghoon Ahn ,  Seung Jae Lee ,  Deokyoung Jung ,  Woojin Lee

    IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53204

    Abstract: A semiconductor device includes a second insulating layer disposed on a substrate and that includes a first trench that extends in a first direction, a first via disposed in the first hole, a first interconnection layer disposed in the first trench on the first via and that has an upwardly upper region, and a third insulating layer disposed on the second insulating layer and that includes a second hole and a second trench connected to the second hole. The first trench has inclined side surfaces such that a width of the first trench increases in a direction toward the substrate, the second hole has inclined side surfaces such that a width of the second hole decreases in the direction toward the substrate, and a lower portion of the second hole is wider than an upper surface of the first interconnection layer.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE SUPPRESSING LEAKAGE CURRENT OF MULTILAYER WIRING STRUCTURES
    16.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE SUPPRESSING LEAKAGE CURRENT OF MULTILAYER WIRING STRUCTURES 有权

    公开(公告)号：US20250014998A1

    公开(公告)日：2025-01-09

    申请号：US18897275

    申请日：2024-09-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoo SHIN ,  Jongmin Baek ,  Sanghoon Ahn ,  Woojin Lee ,  Junhyuk Lim

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A semiconductor integrated circuit device includes a substrate; a transistor on the substrate; an interlayer insulating film on the transistor; an insulating liner on the interlayer insulating film; a first insulating film on the insulating liner; and a first wiring layer on the interlayer insulating film and surrounded by the insulating liner. A height of a top surface of the first insulating film in a vertical direction from a main surface of the interlayer insulating film is different than a height of a top surface of the first wiring layer in the vertical direction. A step exists between the top surfaces of the first wiring layer and the first insulating film. A height of the first insulating film is greater than a height of the first wiring layer. A width of the first wiring layer gradually narrows as the first wiring layer extends upwards along the vertical direction.

    Semiconductor devices having gate isolation layers
    17.
    发明授权
    Semiconductor devices having gate isolation layers 有权

    公开(公告)号：US12034041B2

    公开(公告)日：2024-07-09

    申请号：US18200638

    申请日：2023-05-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seonbae Kim ,  Woojin Lee ,  Seunghoon Choi

    IPC: H01L29/76 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/94

    CPC classification number: H01L29/0649 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/785

    Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

    Semiconductor devices having gate isolation layers
    18.
    发明授权
    Semiconductor devices having gate isolation layers 有权

    公开(公告)号：US11664418B2

    公开(公告)日：2023-05-30

    申请号：US17400358

    申请日：2021-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seonbae Kim ,  Woojin Lee ,  Seunghoon Choi

    IPC: H01L29/76 ,  H01L29/94 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417

    CPC classification number: H01L29/0649 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/785

    Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

Patent Agency Ranking