公开(公告)号：US12034041B2

公开(公告)日：2024-07-09

申请号：US18200638

申请日：2023-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonbae Kim ,  Woojin Lee ,  Seunghoon Choi

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/0649 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/785

Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

公开(公告)号：US11664418B2

公开(公告)日：2023-05-30

申请号：US17400358

申请日：2021-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonbae Kim ,  Woojin Lee ,  Seunghoon Choi

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/0649 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/785

Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.