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    SEMICONDUCTOR DEVICE
    11.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240120392A1

    公开(公告)日：2024-04-11

    申请号：US18244257

    申请日：2023-09-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunjung Lee ,  Donggon Yoo ,  Jeongwon Hwang ,  Sukhoon Kim

    IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device includes a substrate including active regions extending in a first direction; a device isolation layer surrounding the active regions on the substrate; gate structures intersecting the active regions and extending on the substrate in a second direction; source/drain regions on the active regions; contact plugs connected to the source/drain regions, respectively; a vertical buried structure penetrating through at least a portion of the device isolation layer, and in contact with the contact plugs; a vertical insulating layer covering at least a portion of side surfaces of the vertical buried structure; a horizontal buried structure below the vertical buried structure; a first conductive barrier covering at least a portion of an upper surface and side surfaces of the horizontal buried structure; and a metal-semiconductor compound pattern between the vertical buried structure and the first conductive barrier, wherein the vertical buried structure is between source/drain regions.

    Semiconductor device
    12.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11955487B2

    公开(公告)日：2024-04-09

    申请号：US17886878

    申请日：2022-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871

    Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

    Semiconductor device
    14.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11552179B2

    公开(公告)日：2023-01-10

    申请号：US16893795

    申请日：2020-06-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsu Kim ,  Seonghun Park ,  Sunjung Lee ,  Hun Kim ,  Namgil You

    IPC: H01L23/532 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11521 ,  H01L27/11529 ,  H01L29/49 ,  G11C5/02

    Abstract: A semiconductor device includes a peripheral circuit region comprising a first substrate, circuit elements on the first substrate, a first insulating layer covering the circuit elements, and a contact plug passing through the first insulating layer and disposed to be connected to the first substrate; and a memory cell region comprising a second substrate, gate electrodes on the second substrate and stacked in a vertical direction, and channel structures passing through the gate electrodes, wherein the contact plug comprises a metal silicide layer disposed to contact the first substrate and having a first thickness, a first metal nitride layer on the metal silicide layer to contact the metal silicide layer and having a second thickness, greater than the first thickness, a second metal nitride layer on the first metal nitride layer, and a conductive layer on the second metal nitride layer.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    16.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250022875A1

    公开(公告)日：2025-01-16

    申请号：US18615943

    申请日：2024-03-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunjung Lee ,  Donggon Yoo ,  Jeongwon Hwang

    IPC: H01L27/06 ,  H01L23/522 ,  H01L27/02 ,  H01L27/092

    Abstract: The present disclosure relates to three-dimensional semiconductor devices. An example three-dimensional semiconductor device includes a back-side metal layer, a lower active region on the back-side metal layer, the lower active region including a lower channel pattern and a lower source drain pattern connected with the lower channel pattern, an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source drain pattern connected with the upper channel pattern, an interlayer insulating layer enclosing the lower and upper source drain patterns, a penetration conductive pattern extending through the interlayer insulating layer in a vertical direction, and an inhibitor covering a side surface of a lower portion of the penetration conductive pattern. The inhibitor includes a carbon atom.

    INTEGRATED CIRCUIT DEVICE
    17.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20240429303A1

    公开(公告)日：2024-12-26

    申请号：US18658176

    申请日：2024-05-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donggon Yoo ,  Eunhyea Ko ,  Sunjung Lee ,  Yongho Ha ,  Jeongwon Hwang

    IPC: H01L29/45 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

    Abstract: An integrated circuit device includes a substrate, a fin-type active region extending in a first horizontal direction on a first surface of the substrate, a source/drain region on the fin-type active region, an active contact on the source/drain region and electrically connected to the source/drain region, a wiring line extending at a vertical level higher than the source/drain region, a via contact penetrating an insulating layer on the source/drain region and serving as a medium of electrical connection between the active contact and the wiring line, and an adhesive layer between the wiring line and the insulating layer and contacting the wiring line, wherein the via contact includes a top via contact and a bottom via contact, the top via contact includes a metal different from a metal included in the bottom via contact, and the wiring line and the top via contact are in direct contact with each other.

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