公开(公告)号：US09508732B2

公开(公告)日：2016-11-29

申请号：US14746205

申请日：2015-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Hun Lee ,  Ki-Yong Kim ,  Sung-Wook Park ,  Gyu-Yeol Lee

IPC: H01L27/115 ,  H01L29/49 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/823437 ,  H01L21/823443 ,  H01L21/823456 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/788

Abstract: In a semiconductor device, a first gate structure is provided in a cell transistor region and includes a floating gate electrode, a first dielectric layer pattern, and a control gate electrode including a first metal silicide pattern. A second gate structure is provided in a selecting transistor region and includes a first conductive layer pattern, a second dielectric layer pattern, and a first gate electrode including a second metal silicide pattern. A third gate structure is provided in a peripheral circuit region and includes a second conductive layer pattern, a third dielectric layer pattern including opening portions on the second conductive layer pattern, and a second gate electrode including a concavo-convex portion at an upper surface portion thereof and a third metal silicide pattern. The third metal silicide pattern has a uniform thickness.

Abstract translation: 在半导体器件中，第一栅极结构设置在单元晶体管区域中，并且包括浮置栅电极，第一介电层图案和包括第一金属硅化物图案的控制栅电极。 第二栅极结构设置在选择晶体管区域中，并且包括第一导电层图案，第二介电层图案和包括第二金属硅化物图案的第一栅电极。 第三栅极结构设置在外围电路区域中，并且包括第二导电层图案，在第二导电层图案上包括开口部分的第三介电层图案，以及在上表面部分包括凹凸部分的第二栅电极 和第三金属硅化物图案。 第三金属硅化物图案具有均匀的厚度。

公开(公告)号：US11374019B2

公开(公告)日：2022-06-28

申请号：US16837169

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

IPC: H01L23/528 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/423

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

公开(公告)号：US11854975B2

公开(公告)日：2023-12-26

申请号：US17459406

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US20200251417A1

公开(公告)日：2020-08-06

申请号：US16853850

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/11578

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US10692879B2

公开(公告)日：2020-06-23

申请号：US16260388

申请日：2019-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Jong-Ho Park ,  Joon-Hee Lee ,  Hee-Jueng Lee

IPC: H01L27/148 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L27/11575

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.