公开(公告)号：US10916437B2

公开(公告)日：2021-02-09

申请号：US16233399

申请日：2018-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Shin Jang ,  Jong-Min Baek ,  Hoon-Seok Seo ,  Eui-Bok Lee ,  Sung-Jin Kang ,  Vietha Nguyen ,  Deok-Young Jung ,  Sang-Hoon Ahn ,  Hyeok-Sang Oh ,  Woo-Kyung You

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/02 ,  G03F7/004 ,  G03F7/20 ,  G03F7/11 ,  G03F7/075 ,  G03F7/09 ,  H01J37/32

Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.

公开(公告)号：US09812450B2

公开(公告)日：2017-11-07

申请号：US15006265

申请日：2016-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Baek ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Byung-Hee Kim ,  Young-Ju Park ,  Nae-in Lee ,  Kyung-Min Chung

IPC: H01L23/522 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475

Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

公开(公告)号：US08569862B2

公开(公告)日：2013-10-29

申请号：US13792996

申请日：2013-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC: H01L33/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

Abstract translation: 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US20130193552A1

公开(公告)日：2013-08-01

申请号：US13792996

申请日：2013-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC: H01L23/525

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

Abstract translation: 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US11049810B2

公开(公告)日：2021-06-29

申请号：US16448666

申请日：2019-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-Hyun Bark ,  Sang-Hoon Ahn ,  Young-Bae Kim ,  Hyeok-Sang Oh ,  Woo-Jin Lee ,  Hoon-Seok Seo ,  Sung-Jin Kang

IPC: H01L23/48 ,  H01L23/532 ,  H01L29/16 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8234

Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

公开(公告)号：US11037872B2

公开(公告)日：2021-06-15

申请号：US16374901

申请日：2019-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyu-Hee Han ,  Jong-Min Baek ,  Hoon-Seok Seo ,  Sang-Hoon Ahn ,  Woo-Jin Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.

公开(公告)号：US20190311992A1

公开(公告)日：2019-10-10

申请号：US16448666

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-Hyun Bark ,  Sang-Hoon Ahn ,  Young-Bae Kim ,  Hyeok-Sang Oh ,  Woo-Jin Lee ,  Hoon-Seok Seo ,  Sung-Jin Kang

IPC: H01L23/532 ,  H01L23/522 ,  H01L29/16 ,  H01L21/768 ,  H01L23/528 ,  H01L21/311

Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

公开(公告)号：US20190189744A1

公开(公告)日：2019-06-20

申请号：US16274350

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L27/12 ,  H01L27/088 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US10217820B2

公开(公告)日：2019-02-26

申请号：US15632884

申请日：2017-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US09653400B2

公开(公告)日：2017-05-16

申请号：US14984085

申请日：2015-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Yim ,  Woo-Kyung You ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Thomas Oszinda ,  Kee-Young Jun

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns.