公开(公告)号：US20210151432A1

公开(公告)日：2021-05-20

申请号：US16912427

申请日：2020-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/51

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

公开(公告)号：US20200381311A1

公开(公告)日：2020-12-03

申请号：US16707118

申请日：2019-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung Kim ,  Chanhyeong Lee ,  Jinkyu Jang ,  Rakhwan Kim ,  Dongsoo Lee

IPC: H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28

Abstract: A semiconductor device may include a channel pattern stacked on a substrate and a gate electrode on the substrate. The channel pattern includes semiconductor patterns. The gate electrode extends to cross the channel pattern. The gate electrode may include dielectric layers, first work function adjusting patterns, and second work function adjusting patterns. The dielectric layers may enclose the semiconductor patterns, respectively. The first work function adjusting patterns may enclose the dielectric layers, respectively, and the second work function adjusting patterns may enclose the first work function adjusting patterns, respectively. The first work function adjusting patterns may be formed of an aluminum-containing material, and each corresponding one of the first work function adjusting patterns may be in contact with a corresponding one of the second work function adjusting patterns enclosing the corresponding one of the first work function adjusting patterns.

公开(公告)号：US12176290B2

公开(公告)日：2024-12-24

申请号：US17451725

申请日：2021-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungyu Choi ,  Seongheum Choi ,  Daeyong Kim ,  Rakhwan Kim

IPC: H01L23/535 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate; a gate structure extending in a second direction on the substrate, intersecting the active region, and including a gate electrode, source/drain region disposed on the active region on at least one side of the gate structure, a first contact structure connected to the source/drain region; a first gate contact structure disposed on and connected to the gate electrode; a second contact structure disposed on and connected to the first contact structure; and a second gate contact structure disposed on and connected to the first gate contact structure. The second contact structure and/or the second gate contact structure may include an upper metal layer and a metal liner covering a lower surface and side surfaces of the upper metal layer. An external surface of the metal liner may have surface roughness.

公开(公告)号：US20240145387A1

公开(公告)日：2024-05-02

申请号：US18329784

申请日：2023-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemoon Lee ,  Jeongik Kim ,  Sungyu Choi ,  Rakhwan Kim ,  Chunghwan Shin

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/66545

Abstract: A semiconductor device includes a gate structure disposed on a substrate and a contact plug. The contact plug includes a first conductive pattern contacting an upper surface of the first gate structure and a second conductive pattern contacting an upper surface of the first conductive pattern. An upper surface of a central portion of the first conductive pattern is higher than an upper surface of an edge portion of the first conductive pattern. A lower surface of a central portion of the second conductive pattern is higher than a lower surface of an edge portion of the second conductive pattern.

公开(公告)号：US11967554B2

公开(公告)日：2024-04-23

申请号：US18053487

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Kyungwook Kim ,  Rakhwan Kim ,  Seungyong Yoo ,  Eun-Ji Jung

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/45

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45

Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.

公开(公告)号：US20220254779A1

公开(公告)日：2022-08-11

申请号：US17723532

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

公开(公告)号：US20220216339A1

公开(公告)日：2022-07-07

申请号：US17467656

申请日：2021-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyun Lee ,  Dongwoo Kim ,  Daeyong Kim ,  Rakhwan Kim

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L23/522

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes an active region, a plurality of channel layers, gate electrodes, a source/drain region, and a contact structure. The active region is disposed on a substrate and extends in a first direction. The plurality of channel layers are disposed on the active region to be spaced apart from each other vertically. The gate electrodes are disposed on the substrate, intersecting the active region and the plurality of channel layers, extending in a third direction, and surrounding the plurality of channel layers. The source/drain region is disposed on the active region on at least one side of the gate electrodes, and contacting the plurality of channel layers. The contact structure is disposed between the gate electrodes, extending in the second direction, and contacting the source/drain region.

公开(公告)号：US20220199526A1

公开(公告)日：2022-06-23

申请号：US17406887

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Kyu Han ,  Myeongsoo Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522

Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

公开(公告)号：US12176287B2

公开(公告)日：2024-12-24

申请号：US18409447

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Kyu Han ,  Myeongsoo Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092

Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

公开(公告)号：US12080797B2

公开(公告)日：2024-09-03

申请号：US17467656

申请日：2021-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyun Lee ,  Dongwoo Kim ,  Daeyong Kim ,  Rakhwan Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/66553

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes an active region, a plurality of channel layers, gate electrodes, a source/drain region, and a contact structure. The active region is disposed on a substrate and extends in a first direction. The plurality of channel layers are disposed on the active region to be spaced apart from each other vertically. The gate electrodes are disposed on the substrate, intersecting the active region and the plurality of channel layers, extending in a third direction, and surrounding the plurality of channel layers. The source/drain region is disposed on the active region on at least one side of the gate electrodes, and contacting the plurality of channel layers. The contact structure is disposed between the gate electrodes, extending in the second direction, and contacting the source/drain region.