公开(公告)号：US20230361033A1

公开(公告)日：2023-11-09

申请号：US18121456

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooyong Jeon ,  Moorym Choi

IPC: H01L23/528 ,  H01L23/522 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A semiconductor device includes a substrate including a first region and a second region; insulating patterns in the substrate; gate electrodes provided below the substrate and spaced apart from each other in a first direction that is perpendicular to a lower surface of the substrate, the gate electrodes including pad regions arranged in a step shape below the second region; gate contact plugs passing through the pad regions of the gate electrodes, extending in the first direction, and vertically overlapping the insulating patterns; and a peripheral contact plug provided in an outer area of the substrate and extending from a level lower than a level of a lowermost gate electrode of the gate electrodes to a level higher than the lower surface of the substrate; and conductive patterns including a first conductive pattern provided on and connected to the peripheral contact plug, and second conductive patterns provided on and connected to the substrate.

公开(公告)号：US12074128B2

公开(公告)日：2024-08-27

申请号：US17545117

申请日：2021-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym Choi ,  Yoonjo Hwang

IPC: H01L23/00 ,  H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L24/08 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a stack structure having alternating interlayer dielectric layers and gate electrodes, a first insulating layer covering the stack structure, and a second substrate on the stack structure and the first insulating layer, the stack structure being between a bottom surface of the second substrate and the peripheral circuit structure, a second insulating layer on the cell array structure, a first penetration contact penetrating the first insulating layer, the second substrate, and the second insulating layer, and a second penetration contact penetrating the first insulating layer and the second insulating layer, the second penetration contact being spaced apart from the second substrate, and the first and second penetration contacts having widths decreasing with increasing distance from the first substrate.

公开(公告)号：US20230387056A1

公开(公告)日：2023-11-30

申请号：US18057305

申请日：2022-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunsun Jang ,  Jungtae Sung ,  Moorym Choi

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11573 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Disclosed are three-dimensional semiconductor memory devices and electronic systems. The three-dimensional semiconductor memory device includes a first substrate that includes a cell array region and a contact region, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure wherein the cell array structure includes interlayer dielectric layers and gate electrodes that are alternately stacked, a dielectric layer on the stack structure, and a second substrate on the stack structure, a mold structure that penetrates the stack structure and includes a dielectric material, and a first through structure and a second through structure that penetrate the mold structure and are spaced apart from each other.

公开(公告)号：US20220344361A1

公开(公告)日：2022-10-27

申请号：US17667156

申请日：2022-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyong Jeon ,  Moorym Choi

IPC: H01L27/11526 ,  H01L27/11519 ,  H01L23/48 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a peripheral circuit structure including peripheral circuits that are on a semiconductor substrate, and first bonding pads that are electrically connected to the peripheral circuits, and a cell array structure including a memory cell array including memory cells that are three-dimensionally arranged on a semiconductor layer, and second bonding pads that are electrically connected to the memory cell array and are coupled to the first bonding pads. The cell array structure may include a resistor pattern positioned at the same level as the semiconductor layer, a stack including insulating layers and electrodes that are vertically and alternately stacked on the semiconductor layer, and vertical structures penetrating the stack.

公开(公告)号：US11088161B2

公开(公告)日：2021-08-10

申请号：US16036000

申请日：2018-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoung Kim ,  Moorym Choi ,  Dongchan Kim

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/34 ,  G11C16/04 ,  H01L23/532 ,  H01L27/108 ,  G11C29/50 ,  G11C29/04 ,  G11C11/56

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of detecting electrical failure thereof. The three-dimensional semiconductor memory device includes a substrate with a first conductivity including a cell array region and an extension region having different threshold voltages from each other, a stack structure on the substrate and including stacked electrodes, an electrical vertical channel penetrating the stack structure on the cell array region, and a dummy vertical channel penetrating the stack structure on the extension region. The substrate comprises a pocket well having the first conductivity and provided with the stack structure thereon, and a deep well surrounding the pocket well and having a second conductivity opposite to the first conductivity.

公开(公告)号：US10403719B2

公开(公告)日：2019-09-03

申请号：US15723694

申请日：2017-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym Choi ,  Bongyong Lee ,  Junhee Lim

IPC: H01L27/00 ,  H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.

公开(公告)号：US12133381B2

公开(公告)日：2024-10-29

申请号：US17497200

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Taemok Gwon ,  Junhyoung Kim ,  Hyunjae Kim ,  Youngbum Woo ,  Jongin Yun

IPC: H10B41/27 ,  G11C5/06 ,  H01L23/538 ,  H01L29/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H10B43/27

Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.

公开(公告)号：US20240339403A1

公开(公告)日：2024-10-10

申请号：US18405362

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Taeyong Kim ,  Sunil Shim ,  Minhee Lee ,  Yunsun Jang ,  Hayoung Jeong

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, and a lower bonding structure on the first substrate, and a second semiconductor structure including a second substrate, and an upper bonding structure bonded to the lower bonding structure. The second semiconductor structure includes via patterns on the second substrate, a source contact pad including a material different from that of the second substrate, a source contact plug electrically connected to the source contact pad, a source contact via on the source contact pad, and an interconnection line that electrically connects the via patterns to the source contact plug. Lower surfaces of the via patterns are farther from the first substrate than a lower surface of the source contact via, and an upper surface of the second substrate is farther from the first substrate than an upper surface of the source contact pad.

公开(公告)号：US20240334716A1

公开(公告)日：2024-10-03

申请号：US18417970

申请日：2024-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym Choi ,  Seungwoo Paek ,  Sunil Shim ,  Yunsun Jang

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a first semiconductor structure including circuit elements on a first substrate, a lower interconnection structure on the circuit elements, and a lower bonding structure on the lower interconnection structure; and a second semiconductor structure including a second substrate on the first semiconductor structure, separation insulating patterns separating the second substrate, and disposed to be spaced apart from each other, gate electrodes stacked to be spaced apart from each other, separation regions passing through the gate electrodes, and disposed to be spaced apart from each other, channel structures passing through the gate electrodes, an upper interconnection structure below the gate electrodes, and an upper bonding structure bonded to the lower bonding structure, wherein the separation insulating patterns include first separation insulating patterns on the separation regions, and second separation insulating patterns between the channel structures and passing through the second substrate.

公开(公告)号：US20220359442A1

公开(公告)日：2022-11-10

申请号：US17713478

申请日：2022-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Jungtae Sung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/00

Abstract: A semiconductor device includes a first substrate structure including a substrate, circuit elements, and first bonding metal layers, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a plate layer, gate electrodes stacked in a first direction below the plate layer, separation regions penetrating through the gate electrodes and extending in a second direction and spaced apart from each other in the second direction, an insulating region extending from an upper surface of the plate layer and penetrating through the plate layer and at least one of the gate electrodes between the separation regions, and second bonding metal layers connected to the first bonding metal layers. The insulating region has inclined side surfaces such that a width of the insulating region decreases in a direction toward the first substrate structure.