SEMICONDUCTOR DEVICES
    12.
    发明申请

    公开(公告)号:US20220352388A1

    公开(公告)日:2022-11-03

    申请号:US17862909

    申请日:2022-07-12

    Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

    SEMICONDUCTOR DEVICE
    14.
    发明申请

    公开(公告)号:US20250120121A1

    公开(公告)日:2025-04-10

    申请号:US18733327

    申请日:2024-06-04

    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a substrate; an active region extending in a first direction on the substrate; a plurality of channel layers stacked on the active region and spaced apart from each other in a vertical direction perpendicular to the first direction; a gate structure extending on the active region in a second direction perpendicular to the first direction and the vertical direction, and surrounding the plurality of channel layers; a source/drain region provided on at least one side of the gate structure on the active region and electrically connected to the plurality of channel layers; and a plurality of anti-diffusion layers stacked and spaced apart from each other in the vertical direction and extending in the second direction.

    Integrated circuit device
    15.
    发明授权

    公开(公告)号:US12087766B2

    公开(公告)日:2024-09-10

    申请号:US17383749

    申请日:2021-07-23

    CPC classification number: H01L27/0886 H01L29/0669 H01L29/7851

    Abstract: An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.

    Semiconductor devices
    17.
    发明授权

    公开(公告)号:US11211456B2

    公开(公告)日:2021-12-28

    申请号:US16751726

    申请日:2020-01-24

    Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

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