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公开(公告)号：US11777032B2
公开(公告)日：2023-10-03
申请号：US17533499
申请日：2021-11-23
发明人： Youngdae Cho , Sunguk Jang , Sujin Jung , Jungtaek Kim , Sihyung Lee
IPC分类号： H01L29/78 , H01L29/423
CPC分类号： H01L29/785 , H01L29/42356 , H01L29/42392 , H01L2029/7858
摘要： A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.
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公开(公告)号：US20220209013A1
公开(公告)日：2022-06-30
申请号：US17499979
申请日：2021-10-13
发明人： Kihwan Kim , Sunguk Jang , Sujin Jung , Youngdae Cho
摘要： A semiconductor device includes an active region extending in a first direction; a plurality of channel layers on the active region; a gate structure extending in a second direction; and a source/drain region disposed on the active region, and connected to each of the plurality of channel layers, wherein the source/drain region includes a first epitaxial layer having a lower end portion and a sidewall portion extending continuously along lateral surfaces of the plurality of channel layers, the first epitaxial layer doped with a first impurity; and a second epitaxial layer on the first epitaxial layer, having a composition, different from a composition of the first epitaxial layer, and doped with a second impurity, wherein diffusivity of the first impurity in the composition of the first epitaxial layer is lower than the diffusivity that the second impurity would have in the composition of the first epitaxial layer.
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公开(公告)号：US11152517B2
公开(公告)日：2021-10-19
申请号：US16734537
申请日：2020-01-06
发明人： Sunguk Jang , Kihwan Kim , Sujin Jung , Youngdae Cho
IPC分类号： H01L29/08 , H01L29/786 , H01L29/423 , H01L29/78 , H01L29/06 , H01L29/66
摘要： A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.
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公开(公告)号：US12087766B2
公开(公告)日：2024-09-10
申请号：US17383749
申请日：2021-07-23
发明人： Sujin Jung , Kihwan Kim , Sunguk Jang , Youngdae Cho
IPC分类号： H01L27/088 , H01L29/06 , H01L29/78
CPC分类号： H01L27/0886 , H01L29/0669 , H01L29/7851
摘要： An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.
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公开(公告)号：US11211456B2
公开(公告)日：2021-12-28
申请号：US16751726
申请日：2020-01-24
发明人： Sujin Jung , Kihwan Kim , Sunguk Jang , Youngdae Cho
摘要： A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.
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公开(公告)号：US20200381546A1
公开(公告)日：2020-12-03
申请号：US16732864
申请日：2020-01-02
发明人： Youngdae Cho , Sunguk Jang , Sujin Jung , Jungtaek Kim , Sihyung Lee
IPC分类号： H01L29/78 , H01L29/423
摘要： A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.
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公开(公告)号：US12051754B2
公开(公告)日：2024-07-30
申请号：US17862909
申请日：2022-07-12
发明人： Sujin Jung , Junbeom Park , Kihwan Kim , Sunguk Jang , Youngdae Cho
IPC分类号： H01L29/786 , H01L21/02 , H01L29/06 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78696 , H01L21/02532 , H01L21/02603 , H01L21/02645 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/78618
摘要： A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.
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公开(公告)号：US20220352388A1
公开(公告)日：2022-11-03
申请号：US17862909
申请日：2022-07-12
发明人： SUJIN JUNG , Junbeom Park , Kihwan Kim , Sunguk Jang , Youngdae Cho
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/02
摘要： A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.
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公开(公告)号：US10903108B2
公开(公告)日：2021-01-26
申请号：US15869718
申请日：2018-01-12
发明人： Sunguk Jang , Seokhoon Kim , Seung Hun Lee , Yang Xu , Jeongho Yoo , Jongryeol Yoo , Youngdae Cho
IPC分类号： H01L21/76 , H01L21/762 , H01L21/225 , H01L29/423 , H01L21/02 , H01L29/66 , H01L29/165 , H01L29/78
摘要： Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.
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公开(公告)号：US11862733B2
公开(公告)日：2024-01-02
申请号：US17480457
申请日：2021-09-21
发明人： Sunguk Jang , Kihwan Kim , Sujin Jung , Youngdae Cho
IPC分类号： H01L29/786 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/06 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/0673 , H01L29/0843 , H01L29/0847 , H01L29/4232 , H01L29/42392 , H01L29/66545 , H01L29/7851 , H01L29/7854
摘要： A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.
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