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公开(公告)号：US20180350791A1
公开(公告)日：2018-12-06
申请号：US15870143
申请日：2018-01-12
发明人： Jung-Ho Do , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L27/092 , H01L23/522 , H01L23/528 , G06F17/50 , G03F1/36
CPC分类号： H01L27/0207 , G03F1/36 , G06F17/5081 , G06F2217/12 , H01L21/823871 , H01L21/823878 , H01L23/485 , H01L23/5223 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L27/092 , H01L27/11807 , H01L2027/11875 , H01L2027/11881
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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公开(公告)号：US09141751B2
公开(公告)日：2015-09-22
申请号：US13950799
申请日：2013-07-25
发明人： Hyun-Jong Lee , Soo-Han Choi , Jung-Ho Do , Chul-Hong Park , Sang-Pil Sim
IPC分类号： G06F17/50 , H01L21/308
CPC分类号： G06F17/5081 , H01L21/3086
摘要： A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region.
摘要翻译： 形成图案的方法包括限定多个图案，限定接触所述多个图案并对应于所述图案之间的区域的多个倾斜违规图案，将所述多个音高违规图案分类为第一区域和第二区域， 与第一区域相邻，选择第一区域和第二区域中的一个，以及形成被定义为所选择的第一或第二区域的初始图案。 所述选择包括执行以下各项中的至少一个：i）选择接触虚拟图案的区域，ii）选择与一个区域相同类型的区域，以及iii）从所述第一区域选择与外壳的凹部接触的区域，以及 第二个地区。
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13.发明授权公开(公告)号：US11955471B2
公开(公告)日：2024-04-09
申请号：US17584930
申请日：2022-01-26
发明人： Jung-Ho Do , Dal-Hee Lee , Jin-Young Lim , Tae-Joong Song , Jong-Hoon Jung
IPC分类号： H01L27/02 , G06F30/00 , G11C5/06 , G11C8/16 , G11C11/412 , H01L21/768 , H01L27/088 , H01L27/118
CPC分类号： H01L27/0207 , G06F30/00 , G11C5/063 , G11C8/16 , G11C11/412 , H01L21/76895 , H01L27/088 , H01L27/11807 , H01L2027/11875
摘要： An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.
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公开(公告)号：US11887914B2
公开(公告)日：2024-01-30
申请号：US18119560
申请日：2023-03-09
发明人： Jung-Ho Do , Tae-Joong Song , Seung-Young Lee , Jong-Hoon Jung
IPC分类号： H01L23/48 , H01L23/482 , H01L27/02 , H01L27/118 , H01L23/485 , H01L21/768 , G06F30/394 , G06F30/392
CPC分类号： H01L23/481 , G06F30/394 , H01L21/76895 , H01L23/482 , H01L23/485 , H01L27/0207 , H01L27/11807 , G06F30/392 , H01L2027/11875
摘要： An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
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公开(公告)号：USRE49780E1
公开(公告)日：2024-01-02
申请号：US16916419
申请日：2020-06-30
发明人： Taejoong Song , Sanghoon Baek , Sungwe Cho , Jung-Ho Do , Giyoung Yang , Jinyoung Lim
IPC分类号： H01L27/02 , H01L27/118 , G06F30/394
CPC分类号： G06F30/394 , H01L27/0207 , H01L27/11807
摘要： A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
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公开(公告)号：US10803226B2
公开(公告)日：2020-10-13
申请号：US16589360
申请日：2019-10-01
发明人： Jung-Ho Do , Jong-Hoon Jung , Seung-Young Lee , Tae-Joong Song
IPC分类号： G06F30/392 , G03F7/20 , G03F1/70 , G06F30/20 , G06F30/39 , G06F30/398
摘要： An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
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公开(公告)号：US10319668B2
公开(公告)日：2019-06-11
申请号：US15865941
申请日：2018-01-09
发明人： Jung-Ho Do , Tae-Joong Song , Seung-Young Lee , Jong-Hoon Jung
IPC分类号： G06F17/50 , H01L23/48 , H01L27/02 , H01L23/482
摘要： An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
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公开(公告)号：US10217647B2
公开(公告)日：2019-02-26
申请号：US16032127
申请日：2018-07-11
发明人： Jung-Ho Do , Jonghoon Jung , Sanghoon Baek , Seungyoung Lee , Taejoong Song , Jinyoung Lim
IPC分类号： H01L21/8238 , H01L21/3213
摘要： A method of manufacturing a semiconductor device may include forming active patterns, forming a polygonal mask pattern having a first width and a second width on the active patterns, forming an active region by executing a first etching process using the mask pattern, forming a first cutting mask for removing a first corner rounding in which a width of the active region is the first width, removing the first corner rounding by executing a second etching process using the first cutting mask, forming a second cutting mask for removing a second corner rounding in which the width of the active region is changed from the first width to the second width, and executing a third etching process using the second cutting mask.
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公开(公告)号：US09767248B2
公开(公告)日：2017-09-19
申请号：US14844420
申请日：2015-09-03
发明人： Taejoong Song , Jung-Ho Do , Changho Han
CPC分类号： G06F17/5081 , G01R31/2882 , G06F2217/14
摘要： A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type of a cross coupled structure (XC) and a second type of the XC on a substrate of the semiconductor device, forming a plurality of first inverters in which the first type of the XC is activated in the a plurality of the standard cells and a plurality of second inverters in which the second type of the XC is activated in the a plurality of the standard cells and estimating an electrical characteristic of the first type of the XC or the second type of the XC by measuring a magnitude of a signal delay of the plurality of the first inverters or the plurality of the second inverters.
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20.发明授权公开(公告)号：US09716106B2
公开(公告)日：2017-07-25
申请号：US15232223
申请日：2016-08-09
发明人： Sang-hoon Baek , Sang-kyu Oh , Jung-Ho Do , Sun-young Park , Seung-young Lee , Hyo-sig Won
IPC分类号： H01L27/118 , H01L27/02 , H01L27/092 , H01L29/423 , H01L29/78 , H01L29/66
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/0924 , H01L29/42384 , H01L29/6681 , H01L29/785 , H01L2027/11875
摘要： An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.
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