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    Capacitor structures having supporting patterns and methods of forming the same
    12.
    发明授权
    Capacitor structures having supporting patterns and methods of forming the same 有权
    具有支撑图案的电容器结构及其形成方法

    公开(公告)号：US09171670B2

    公开(公告)日：2015-10-27

    申请号：US13761294

    申请日：2013-02-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun-Hee Lim

    IPC: H01G7/00 ,  H01G4/018 ,  H01G4/01 ,  H01G4/33 ,  H01G4/38 ,  H01G4/08 ,  H01L27/108 ,  H01L49/02

    CPC classification number: H01G4/018 ,  H01G4/01 ,  H01G4/085 ,  H01G4/33 ,  H01G4/38 ,  H01L27/10852 ,  H01L28/91 ,  Y10T29/435

    Abstract: A method of forming a capacitor structure includes forming a mold layer on a substrate, in which the substrate includes a plurality of plugs therein, partially removing the mold layer to form a plurality of openings, in which the plugs are exposed by the openings, forming a plurality of lower electrodes filling the openings, in which the lower electrodes have a pillar shape, removing an upper portion of the mold layer to expose upper portions of the lower electrodes, forming a supporting pattern on exposed upper sidewalls of the lower electrodes and on the mold layer, removing the mold layer, and sequentially forming a dielectric layer and an upper electrode on the lower electrodes and the supporting pattern.

    Abstract translation: 形成电容器结构的方法包括在基板上形成模具层，其中基板在其中包括多个塞子，部分地移除模具层以形成多个开口，其中插头由开口暴露，形成 填充开口的多个下电极，其中下电极具有柱形，去除模具层的上部以暴露下电极的上部，在下电极的暴露的上侧壁上形成支撑图案，并且在 模具层，去除模具层，并且在下电极和支撑图案上依次形成电介质层和上电极。

    Semiconductor devices
    13.
    发明授权
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US09082647B2

    公开(公告)日：2015-07-14

    申请号：US14465982

    申请日：2014-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Ho Jang ,  Dong-Jin Lee ,  Bong-Soo Kim ,  Jun-Hee Lim ,  Joon Han

    IPC: H01L27/108 ,  H01L27/12 ,  H01L27/13

    CPC classification number: H01L27/108 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10855 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/12 ,  H01L27/13 ,  H01L29/785

    Abstract: There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon.

    Abstract translation: 提供了一种半导体器件。 半导体器件可以包括多个触点插头，绝缘层图案，金属氧化物层图案，金属图案和金属线。 接触插头接触基板。 绝缘层图案形成在接触插塞之间，并且具有比接触插塞低的顶表面。 金属氧化物层图案形成在绝缘层图案上，并且具有比氧化硅更高的介电常数。 金属图案形成在金属氧化物层图案上并接触接触插塞的侧壁。 金属线接触接触插塞的顶表面和金属图案并在其上延伸。

    Semiconductor device
    14.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09070701B2

    公开(公告)日：2015-06-30

    申请号：US13780146

    申请日：2013-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun-Hee Lim ,  Chan-Seung Hwang

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/91

    Abstract: A semiconductor device is provided. The semiconductor device includes first and second storage electrodes formed to be spaced apart from each other on a substrate, an insulating continuous support pattern connected to top surfaces of the first and second storage electrodes, a storage dielectric layer formed to cover the first and second storage electrodes and the continuous support pattern, and a plate electrode formed on the storage dielectric layer. The continuous support pattern includes a first contact part connected to the top surface of the first storage electrode, a second contact part connected to the top surface of the second storage electrode, and a connection part connecting the first and second contact parts with each other.

    Abstract translation: 提供半导体器件。 半导体器件包括在基板上形成为彼此间隔开的第一和第二存储电极，连接到第一和第二存储电极的顶表面的绝缘连续支撑图案，形成为覆盖第一和第二存储器 电极和连续支撑图案，以及形成在存储介质层上的平板电极。 连续支撑图案包括连接到第一存储电极的顶表面的第一接触部分，连接到第二存储电极的顶表面的第二接触部分和将第一和第二接触部分彼此连接的连接部分。

    Vertical semiconductor devices
    16.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US10680011B2

    公开(公告)日：2020-06-09

    申请号：US16263417

    申请日：2019-01-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-Hwan Lee ,  Chang-Seok Kang ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565

    Abstract: A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    17.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20150008530A1

    公开(公告)日：2015-01-08

    申请号：US14312777

    申请日：2014-06-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Won-Kyung Park ,  Ki-Jae Hur ,  Hyeong-Sun Hong ,  Se-Young Kim ,  Jun-Hee Lim

    IPC: H01L27/108 ,  H01L21/28 ,  H01L29/06 ,  H01L21/265 ,  H01L27/092 ,  H01L21/8238

    CPC classification number: H01L27/10897 ,  H01L21/265 ,  H01L21/28158 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/0649

    Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

    Abstract translation: 提供一种半导体器件。 单元区域设置在基板中。 单元区域包括存储单元。 外围区域设置在基板中。 外围区域与细胞区域相邻。 外围区域具有沟槽隔离，第一有源区和第二有源区。 沟槽隔离被插入在第一有源区和第二有源区之间。 公共栅极图案设置在周边区域上。 公共栅极图案沿第一方向延伸并且部分地与第一有源区域，第二有源区域和沟槽隔离部分重叠。 掩埋导电图案被沟槽隔离封闭。 掩埋导电图案沿与第一方向交叉的第二方向延伸。 掩埋导电图案的顶表面比公共栅极图案的底表面低。

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