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    Semiconductor device and method of forming the same
    6.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US09240415B2

    公开(公告)日：2016-01-19

    申请号：US14312777

    申请日：2014-06-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Won-Kyung Park ,  Ki-Jae Hur ,  Hyeong-Sun Hong ,  Se-Young Kim ,  Jun-Hee Lim

    IPC: H01L21/70 ,  H01L27/108 ,  H01L29/06 ,  H01L21/265 ,  H01L21/28

    CPC classification number: H01L27/10897 ,  H01L21/265 ,  H01L21/28158 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/0649

    Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

    Abstract translation: 提供半导体器件。 单元区域设置在基板中。 单元区域包括存储单元。 外围区域设置在基板中。 外围区域与细胞区域相邻。 外围区域具有沟槽隔离，第一有源区和第二有源区。 沟槽隔离被插入在第一有源区和第二有源区之间。 公共栅极图案设置在周边区域上。 公共栅极图案沿第一方向延伸并且部分地与第一有源区域，第二有源区域和沟槽隔离部分重叠。 掩埋导电图案被沟槽隔离封闭。 掩埋导电图案沿与第一方向交叉的第二方向延伸。 掩埋导电图案的顶表面比公共栅极图案的底表面低。

    Vertical memory devices
    7.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11056645B2

    公开(公告)日：2021-07-06

    申请号：US16509836

    申请日：2019-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Hwan Lee ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A vertical memory device includes gate electrodes on a substrate and a first structure. The gate electrodes may be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate. The first structure extends through the gate electrodes in the first direction, and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable resistance structure may include quantum dots (QDs) therein.

    VERTICAL SEMICONDUCTOR DEVICES
    8.
    发明申请
    VERTICAL SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190393239A1

    公开(公告)日：2019-12-26

    申请号：US16263417

    申请日：2019-01-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KYUNG-HWAN LEE ,  Chang-Seok Kang ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

    IPC: H01L27/11582 ,  H01L27/11565

    Abstract: A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

    Vertical semiconductor devices
    10.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US10861874B2

    公开(公告)日：2020-12-08

    申请号：US16445433

    申请日：2019-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Hwan Lee ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762

    Abstract: A vertical semiconductor device includes conductive pattern structures extending in a first direction, a trench between two adjacent conductive pattern structures in a second direction crossing the first direction, a memory layer disposed on sidewalls of the trench, first insulation layers disposed in the trench and spaced apart from each other in the first direction, channel patterns disposed on the memory layer and in the trench and spaced apart from each other in the first direction, and etch stop layer patterns disposed in the trench. Each conductive pattern structure includes conductive patterns and insulation layers alternately stacked on an upper surface of the substrate. Each etch stop layer pattern is disposed between a corresponding first insulation layer and the blocking dielectric layer. Etch stop layer patterns are spaced apart from each other in the first direction.

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