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    Vertical memory devices
    3.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11056645B2

    公开(公告)日：2021-07-06

    申请号：US16509836

    申请日：2019-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Hwan Lee ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A vertical memory device includes gate electrodes on a substrate and a first structure. The gate electrodes may be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate. The first structure extends through the gate electrodes in the first direction, and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable resistance structure may include quantum dots (QDs) therein.

    Vertical semiconductor devices
    5.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US10861874B2

    公开(公告)日：2020-12-08

    申请号：US16445433

    申请日：2019-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Hwan Lee ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762

    Abstract: A vertical semiconductor device includes conductive pattern structures extending in a first direction, a trench between two adjacent conductive pattern structures in a second direction crossing the first direction, a memory layer disposed on sidewalls of the trench, first insulation layers disposed in the trench and spaced apart from each other in the first direction, channel patterns disposed on the memory layer and in the trench and spaced apart from each other in the first direction, and etch stop layer patterns disposed in the trench. Each conductive pattern structure includes conductive patterns and insulation layers alternately stacked on an upper surface of the substrate. Each etch stop layer pattern is disposed between a corresponding first insulation layer and the blocking dielectric layer. Etch stop layer patterns are spaced apart from each other in the first direction.

    Coupling member and electronic device including the same
    6.
    发明授权
    Coupling member and electronic device including the same 有权

    公开(公告)号：US10168736B2

    公开(公告)日：2019-01-01

    申请号：US15235918

    申请日：2016-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyung-Woo Lee ,  Hwan-Seok Choi ,  Kyung-Hwan Lee ,  Jong-Cheon Wee

    IPC: G06F1/16

    Abstract: A coupling member that is attachable to/detachable from a housing of an electronic device while making the housing wearable on a user's body, and an electronic device including the coupling member is provided. The electronic device includes a band member that is configured to come in contact with a user's body portion, a slide member that is mounted on the band member, and is bound to a portion of the housing in a state where the coupling member is mounted on the housing, an opening that is formed in the slide member, a locking member that is disposed on the band member, and a locking protrusion that is formed on a locking member. The locking protrusion appears to the outside of the slide member through the opening according to the reciprocating of the locking member, and the coupling member is bound to the housing.

    Band mounting structure and wearable electronic device including the same
    7.
    发明授权
    Band mounting structure and wearable electronic device including the same 有权

    公开(公告)号：US10114414B2

    公开(公告)日：2018-10-30

    申请号：US15861316

    申请日：2018-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Hwan Lee ,  Jin Yong Kim ,  Hyungwoo Lee ,  Seungyeon Kim ,  You-Sub Shim ,  Jong-Chul Choi

    IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  H01Q1/22 ,  G04G17/04 ,  G06F3/14 ,  G04R60/12 ,  H01Q1/27 ,  G06F3/01

    Abstract: An electronic device includes a housing including a first plate, a second plate, and a side member a first band detachably mounted to the side member, and shaped to wrap around a wrist of a user; a display exposed through the first plate; a processor a memory and a mounting structure configured to connect the first band to the side member. The mounting structure includes a recessed structure formed in the side member, the recessed structure having a first surface, a second surface, a first hole formed in the first surface, and a second hole formed in the second surface, and facing the first hole, in which an imaginary line extending from the first hole to the second hole defines a first axis; a rotating member positioned to rotate around the first axis, the rotating member having a through-hole that has an inner screw surface centered around the first axis; a first rod extending along the first axis through a first portion of the first band, in which the first rod has a first end inserted into the first hole, and a second end held by the rotating member such that the first rod does not move along the first axis while the rotating member rotates; and a second rod extending along the first axis through a second portion of the first band. The second rod has: a third end rotatably inserted into the second hole; and an external screw surface engaged with the inner screw surface of the rotating member such that the second rod moves along the first axis while the rotating member rotates.

    Vertical semiconductor devices
    10.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US10680011B2

    公开(公告)日：2020-06-09

    申请号：US16263417

    申请日：2019-01-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-Hwan Lee ,  Chang-Seok Kang ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565

    Abstract: A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

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