公开(公告)号：US10367002B2

公开(公告)日：2019-07-30

申请号：US15288517

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Il Chang ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L21/265 ,  H01L27/11556 ,  H01L29/78 ,  H01L27/1157

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US08895393B2

公开(公告)日：2014-11-25

申请号：US13892756

申请日：2013-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Sung Sim ,  Jung-Dal Choi

IPC: H01L21/336 ,  G11C16/26 ,  H01L21/8234 ,  G11C16/04 ,  H01L27/115 ,  G11C16/14 ,  H01L29/788

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L21/823481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66666 ,  H01L29/7881

Abstract: In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

Abstract translation: 在半导体器件和形成这种器件的方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。 在基板上设置多个层间电介质层。 提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间介电层之间。 半导体材料的垂直沟道沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案，每个栅极图案和垂直沟道之间的栅极绝缘层将栅极图案与垂直沟道绝缘，垂直沟道 在包括半导体区域的接触区域处与衬底接触。

公开(公告)号：US11152390B2

公开(公告)日：2021-10-19

申请号：US16903070

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L21/265 ,  H01L27/11556

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US10700092B2

公开(公告)日：2020-06-30

申请号：US16441163

申请日：2019-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L21/265 ,  H01L27/11556

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US09385138B2

公开(公告)日：2016-07-05

申请号：US14529157

申请日：2014-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Sung Sim ,  Jung-Dal Choi

IPC: H01L27/115 ,  H01L29/788 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L21/823481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66666 ,  H01L29/7881

Abstract: In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

Abstract translation: 在半导体器件和形成这种器件的方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。 在基板上设置多个层间电介质层。 提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间介电层之间。 半导体材料的垂直沟道沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案，每个栅极图案和垂直沟道之间的栅极绝缘层将栅极图案与垂直沟道绝缘，垂直沟道 在包括半导体区域的接触区域处与衬底接触。

公开(公告)号：US20150064865A1

公开(公告)日：2015-03-05

申请号：US14529157

申请日：2014-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Sung Sim ,  Jung-Dal Choi

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/04 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L21/823481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66666 ,  H01L29/7881

Abstract: In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

公开(公告)号：US20200312878A1

公开(公告)日：2020-10-01

申请号：US16903070

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-il CHANG ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L21/265 ,  H01L27/11556

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.