公开(公告)号：US11742351B2

公开(公告)日：2023-08-29

申请号：US17384920

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US11557656B2

公开(公告)日：2023-01-17

申请号：US17024813

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghan Lee ,  Wandon Kim ,  Jaeyeol Song ,  Jeonghyuk Yim ,  HyungSuk Jung

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

公开(公告)号：US20200381432A1

公开(公告)日：2020-12-03

申请号：US16718799

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Lee ,  Jonghan Lee ,  Seonghwa Park ,  Jongha Park ,  Jaehoon Woo ,  Dabok Jeong

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region proximate a boundary between the first region and the second region.

公开(公告)号：US10079186B2

公开(公告)日：2018-09-18

申请号：US15273933

申请日：2016-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangyub Ie ,  Minwoo Song ,  Jonghan Lee ,  Hyungsuk Jung ,  Hyeri Hong

IPC: H01L23/58 ,  H01L21/66 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L22/34 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L22/14 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device includes forming first and second fin patterns in an active region and in a measurement region of a substrate, respectively, the measurement region being different from the active region, forming first and second gate electrodes to cross the first and second fin patterns, respectively, and measuring a contact potential difference (Vcpd) of the second gate electrode to determine a threshold voltage of the first gate electrode based on the measured contact potential difference (Vcpd).