公开(公告)号：US20200381432A1

公开(公告)日：2020-12-03

申请号：US16718799

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Lee ,  Jonghan Lee ,  Seonghwa Park ,  Jongha Park ,  Jaehoon Woo ,  Dabok Jeong

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region proximate a boundary between the first region and the second region.

公开(公告)号：US11664379B2

公开(公告)日：2023-05-30

申请号：US17321760

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Lee ,  Jonghan Lee ,  Seonghwa Park ,  Jongha Park ,  Jaehoon Woo ,  Dabok Jeong

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region proximate a boundary between the first region and the second region.

公开(公告)号：US20210272957A1

公开(公告)日：2021-09-02

申请号：US17321760

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Lee ,  Jonghan Lee ,  Seonghwa Park ,  Jongha Park ,  Jaehoon Woo ,  Dabok Jeong

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region proximate a boundary between the first region and the second region.

公开(公告)号：US11043495B2

公开(公告)日：2021-06-22

申请号：US16718799

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Lee ,  Jonghan Lee ,  Seonghwa Park ,  Jongha Park ,  Jaehoon Woo ,  Dabok Jeong

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region proximate a boundary between the first region and the second region.