公开(公告)号：US09379115B2

公开(公告)日：2016-06-28

申请号：US14089075

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Chol

IPC: H01L27/105 ,  H01L27/06 ,  H01L27/115 ,  H01L49/02

CPC classification number: H01L27/1052 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/20

Abstract: In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

公开(公告)号：US20150228660A1

公开(公告)日：2015-08-13

申请号：US14692197

申请日：2015-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/764

CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

Abstract translation: 公开了非易失性存储器件及其制造方法。 非易失性存储器件包括限定衬底中的有源部分和设置在衬底上的栅极结构的器件隔离图案。 有源部分在第一方向上彼此间隔开，并且在垂直于第一方向的第二方向上延伸。 栅极结构在第二方向上彼此间隔开并且在第一方向上延伸。 每个器件隔离图案包括第一气隙，并且第一气隙的顶表面和底表面中的每一个在沿着第二方向截取的截面图中具有波形。

公开(公告)号：US20140322911A1

公开(公告)日：2014-10-30

申请号：US14328496

申请日：2014-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HO LEE ,  Keonsoo Kim ,  Hyunchul Back ,  Jinhyun Shin ,  Seungwook Choi

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897

Abstract: A method of forming a semiconductor device may include forming a contact mold layer on a substrate; forming an interconnection mold layer on the contact mold layer that includes a material having an etching selectivity with respect to the contact mold layer; forming grooves in the interconnection mold layer that extend in a first direction and expose the contact mold layer; forming holes in the contact mold layer connected to the grooves by etching a part of the contact mold layer exposed by the groove; and forming contact portions in the holes and interconnections in the groove. A diffusion coefficient of mobile atoms in the contact mold layer is greater than a diffusion coefficient of mobile atoms in a nitride.

Abstract translation: 形成半导体器件的方法可以包括在基片上形成接触模层; 在所述接触模层上形成互连模层，所述互连模层包括相对于所述接触模层具有蚀刻选择性的材料; 在所述互连模制层中形成沿第一方向延伸并暴露所述接触模制层的凹槽; 通过蚀刻由凹槽露出的接触模具层的一部分，在连接到凹槽的接触模层中形成孔; 并且在孔中形成接触部分和凹槽中的互连。 接触模具层中的移动原子的扩散系数大于氮化物中的移动原子的扩散系数。

公开(公告)号：US20140021524A1

公开(公告)日：2014-01-23

申请号：US13915158

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

IPC: H01L29/06

CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

公开(公告)号：US10153295B2

公开(公告)日：2018-12-11

申请号：US15613602

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

公开(公告)号：US09911745B2

公开(公告)日：2018-03-06

申请号：US15426081

申请日：2017-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Youngwoo Kim ,  Jinhyun Shin ,  Jung Hoon Lee

IPC: H01L27/11551 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11 ,  H01L27/11556 ,  H01L27/108 ,  H01L27/11529 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/115 ,  H01L21/8234 ,  H01L27/11597

CPC classification number: H01L27/11551 ,  H01L21/26506 ,  H01L21/28158 ,  H01L21/823462 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/11246 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/1083 ,  H01L29/42368

Abstract: A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.

公开(公告)号：US09773795B2

公开(公告)日：2017-09-26

申请号：US14692197

申请日：2015-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

IPC: H01L27/11 ,  H01L27/11521 ,  H01L29/06 ,  H01L21/764 ,  H01L29/788 ,  H01L27/11524 ,  H01L27/11517 ,  H01L27/11563 ,  H01L21/762

CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

公开(公告)号：US08975684B2

公开(公告)日：2015-03-10

申请号：US13915158

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

IPC: H01L29/06 ,  H01L21/764 ,  H01L29/788 ,  H01L27/115 ,  H01L21/762

CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

Abstract translation: 公开了非易失性存储器件及其制造方法。 非易失性存储器件包括限定衬底中的有源部分和设置在衬底上的栅极结构的器件隔离图案。 有源部分在第一方向上彼此间隔开，并且在垂直于第一方向的第二方向上延伸。 栅极结构在第二方向上彼此间隔开并且在第一方向上延伸。 每个器件隔离图案包括第一气隙，并且第一气隙的顶表面和底表面中的每一个在沿着第二方向截取的截面图中具有波形。

公开(公告)号：US08969215B2

公开(公告)日：2015-03-03

申请号：US14079282

申请日：2013-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Jinhyun Shin

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/115

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11519

Abstract: Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby are provided. Two photolithography processes and two spacer processes are performed to provide final patterns that have a pitch that is smaller than a limitation of photolithography process. Furthermore, since initial patterns are formed to have line and pad portions simultaneously by performing a first photolithography process, there is no necessity to perform an additional photolithography process for forming the pad portion.

Abstract translation: 提供制造半导体器件的方法和由此制造的半导体器件。 执行两个光刻工艺和两个间隔器工艺以提供具有小于光刻工艺限制的间距的最终图案。 此外，由于通过执行第一光刻工艺来形成初始图案以同时具有线和焊盘部分，因此不需要执行用于形成焊盘部分的附加光刻工艺。

公开(公告)号：US20140154885A1

公开(公告)日：2014-06-05

申请号：US14079282

申请日：2013-11-13

Applicant: Samsung Electronics Co., Ltd

Inventor： Jae-Hwang Sim ,  Jinhyun Shin

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11519

Abstract: Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby are provided. Two photolithography processes and two spacer processes are performed to provide final patterns that have a pitch that is smaller than a limitation of photolithography process. Furthermore, since initial patterns are formed to have line and pad portions simultaneously by performing a first photolithography process, there is no necessity to perform an additional photolithography process for forming the pad portion.

Abstract translation: 提供制造半导体器件的方法和由此制造的半导体器件。 执行两个光刻工艺和两个间隔器工艺以提供具有小于光刻工艺限制的间距的最终图案。 此外，由于通过执行第一光刻工艺来形成初始图案以同时具有线和焊盘部分，因此不需要执行用于形成焊盘部分的附加光刻工艺。