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    Wiring boards and semiconductor modules including the same
    14.
    发明授权
    Wiring boards and semiconductor modules including the same 有权
    接线板和包括其的半导体模块

    公开(公告)号：US09560767B2

    公开(公告)日：2017-01-31

    申请号：US13734322

    申请日：2013-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yonghoon Kim ,  Seung Hwan Kim ,  Heeseok Lee

    IPC: H05K1/16 ,  H05K1/18 ,  H01L49/02 ,  H05K3/46

    CPC classification number: H05K1/185 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K3/4608 ,  H05K2201/0979 ,  H05K2201/10015

    Abstract: A wiring board includes a metal core including a first surface and a second surface facing each other and a first portion and a second portion disposed on the first and second surfaces, respectively. The first and second portions each include a plurality of insulating layers and a plurality of wiring layers stacked in an alternating manner. At least one capacitor is disposed in at least one interior region. The at least one capacitor includes first and second electrodes. The at least one interior region exposes a portion of the metal core and a portion of at least one of the first and second portions adjacent to the metal core and at least one first via electrically connects one of the wiring layers of the first portion with the first and second electrodes.

    Abstract translation: 布线板包括金属芯，该金属芯包括彼此面对的第一表面和第二表面，以及分别设置在第一表面和第二表面上的第一部分和第二部分。 第一和第二部分各自包括交替堆叠的多个绝缘层和多个布线层。 至少一个电容器设置在至少一个内部区域中。 所述至少一个电容器包括第一和第二电极。 所述至少一个内部区域暴露所述金属芯的一部分，并且所述第一和第二部分中的至少一个的一部分与所述金属芯相邻，并且至少一个第一通孔将所述第一部分的所述布线层中的一个与 第一和第二电极。

    SEMICONDUCTOR PACKAGE
    15.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250132271A1

    公开(公告)日：2025-04-24

    申请号：US18912124

    申请日：2024-10-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyojin Hwang ,  Junso Pak ,  Heeseok Lee

    IPC: H01L23/64 ,  H01L23/498 ,  H01L25/16 ,  H05K1/11 ,  H05K1/18

    Abstract: A semiconductor package includes a printed circuit board including a circuit pattern and a silicon capacitor connected to the circuit pattern, a semiconductor chip mounted on the printed circuit board, and an external connection terminal attached below the printed circuit board, wherein the silicon capacitor is a stacked structure of a plurality of substrate structures, each of the plurality of substrate structures includes a silicon substrate, a capacitor structure, a via electrode penetrating through the silicon substrate around the capacitor structure, an upper bump pad disposed on top of the via electrode, and a lower bump pad disposed below the via electrode, and, in the plurality of substrate structures, neighboring silicon substrates are bonded to each other through the upper bump pad and the lower bump pad facing each other.

    Semiconductor package including composite molding structure
    16.
    发明授权
    Semiconductor package including composite molding structure 有权

    公开(公告)号：US11908774B2

    公开(公告)日：2024-02-20

    申请号：US17850504

    申请日：2022-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heeseok Lee ,  Yunhyeok Im

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/40

    CPC classification number: H01L23/481 ,  H01L23/3135 ,  H01L23/498 ,  H01L25/105 ,  H01L2023/4087 ,  H01L2225/1011 ,  H01L2225/1041

    Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

    Semiconductor package including a dualized signal wiring structure
    20.
    发明授权
    Semiconductor package including a dualized signal wiring structure 有权

    公开(公告)号：US12224260B2

    公开(公告)日：2025-02-11

    申请号：US17542667

    申请日：2021-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heejung Choi ,  Heeseok Lee ,  Junso Pak ,  Bongwee Yu

    IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

    Abstract: A semiconductor package including: a plurality of lower pads; an upper pad; a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad; a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad, wherein the first lower pad and the second lower pad are separated from each other by a minimum distance between the plurality of lower pads.

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