公开(公告)号：US11968824B2

公开(公告)日：2024-04-23

申请号：US18137169

申请日：2023-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Sungwoo Kim ,  Bongsoo Kim

IPC: H01L27/10 ,  H01L21/768 ,  H10B12/00

CPC classification number: H10B12/485 ,  H01L21/76829 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US20230255021A1

公开(公告)日：2023-08-10

申请号：US18137169

申请日：2023-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H10B12/00 ,  H01L21/768

CPC classification number: H10B12/485 ,  H01L21/76829 ,  H10B12/09 ,  H10B12/315 ,  H10B12/0335

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US11678478B2

公开(公告)日：2023-06-13

申请号：US17667697

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76829 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US11616066B2

公开(公告)日：2023-03-28

申请号：US17384347

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US11355445B2

公开(公告)日：2022-06-07

申请号：US17007945

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Doohwan Lee ,  Taeho Ko ,  Bongsoo Kim ,  Seokbong Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01P3/08 ,  H01P11/00 ,  H01L23/29

Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

公开(公告)号：US11264392B2

公开(公告)日：2022-03-01

申请号：US16832268

申请日：2020-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L29/00 ,  H01L27/108

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US11088143B2

公开(公告)日：2021-08-10

申请号：US16896470

申请日：2020-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US20250105159A1

公开(公告)日：2025-03-27

申请号：US18823171

申请日：2024-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pyunghwa Han ,  Dahee Kim ,  Bongsoo Kim ,  Chobi Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package includes a first wiring structure, an extension structure disposed on the first wiring structure, including an extension base layer and a plurality of via structures, and having a mounting space passing through the extension base layer. The plurality of via structures include a plurality of via connection patterns, a semiconductor chip disposed in the mounting space and electrically connected to the first wiring structure, a filling insulating layer filling the mounting space, and a second wiring structure disposed on the extension structure and the filling insulating layer and electrically connected to the first wiring structure. Lowermost via connection patterns, among the plurality of via connection patterns, include a plurality of first lower connection pads, and the extension base layer includes base dams respectively passing through the plurality of first lower connection pads.

公开(公告)号：US12232259B2

公开(公告)日：2025-02-18

申请号：US18107129

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoo Kim ,  Gyeongmin Jin ,  Hakjoon Kim ,  Jaebum Lee

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/34

Abstract: An electronic device according to an embodiment may include: a Printed Circuit Board (PCB) including a first face and a second face; a semiconductor chip mounted on the second face; a conductive pad disposed on the second face; a solder resist layer disposed on the second face and including an aperture; an arc-shaped opening having an inner diameter and an outer diameter, disposed along an outer periphery of the conductive pad and in the aperture; and at least one external terminal disposed on the semiconductor chip and bonded to the conductive pad. The conductive pad may include: a first region having a smaller diameter than the outer diameter; and at least one second region extending from the first region in a first outer circumferential direction, and located at least in part between both ends of the opening. In addition, various embodiments recognized through the specification may also be possible.

公开(公告)号：US11917815B2

公开(公告)日：2024-02-27

申请号：US18123736

申请日：2023-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H10B12/00 ,  H01L27/108 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/5283 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.