公开(公告)号：US20240355883A1

公开(公告)日：2024-10-24

申请号：US18385537

申请日：2023-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyumin YOO ,  Myung Gil KANG ,  Dongwon KIM ,  Jongsu KIM ,  Beomjin PARK ,  Byeonghee SON

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/0653

Abstract: A semiconductor device includes a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are stacked to be spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a blocking layer between the source/drain pattern and the active pattern, wherein the source/drain pattern includes a protruding side surface protruding toward the semiconductor patterns, the blocking layer includes silicon-germanium (SiGe), and a germanium concentration of the blocking layer is higher than a germanium concentration of the source/drain pattern.

公开(公告)号：US20240204054A1

公开(公告)日：2024-06-20

申请号：US18589893

申请日：2024-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Noh Yeong PARK ,  Dong Il BAE ,  Beomjin PARK

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/1033 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/42372

Abstract: Disclosed are semiconductor devices and/or method of fabricating the same. The semiconductor device comprises a substrate including first and second regions, a first active pattern on the first region and including a pair of first source/drain patterns and a first channel pattern including first semiconductor patterns, a second active pattern on the second region and including a pair of second source/drain patterns and a second channel pattern including second semiconductor patterns, a support pattern between two vertically adjacent first semiconductor patterns, and a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern. A channel length of the first channel pattern is greater than that of the second channel pattern. A ratio of a width of the support pattern to the channel length of the first channel pattern is in a range of 0.05 to 0.2.

公开(公告)号：US20240178293A1

公开(公告)日：2024-05-30

申请号：US18228824

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyumin YOO ,  Beomjin PARK ,  Myung Gil KANG ,  Dongwon KIM ,  Younggwon KIM

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/7848

Abstract: Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns spaced apart from and vertically stacked on each other, a source/drain pattern connected to the semiconductor patterns having a p-type, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate dielectric layer between the gate electrode and the semiconductor patterns and including an inner gate dielectric layer adjacent to the inner electrode and an outer gate dielectric layer that extends from bottom to lateral surfaces of the outer electrode. The outer electrode and the outer gate dielectric layer have an inverted T shape.

公开(公告)号：US20230422501A1

公开(公告)日：2023-12-28

申请号：US18190876

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon KWON ,  Beomjin PARK ,  Boun YOON

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes a substrate, circuit devices on the substrate, lower interconnection lines electrically connected to the circuit devices, a peripheral region insulating layer covering the lower interconnection lines, a source structure on the peripheral region insulating layer, gate electrodes stacked and spaced apart from each other in a first direction on the source structure, channel structures penetrating through the gate electrodes and each including a channel layer, contact plugs penetrating through the gate electrodes and the source structure, extending in the first direction, and connected to a portion of the lower interconnection lines, and spacer layers between the contact plugs and the source structure and including a material different from a material of the insulating layer in the peripheral region, wherein each of the spacer layers has a first width on an upper surface and has a second width greater than the first width on a lower surface.

公开(公告)号：US20230051602A1

公开(公告)日：2023-02-16

申请号：US17725180

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Hyojin Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Sangmoon Lee ,  Dongwon Kim ,  Keun Hwi Cho

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate and extending in a first direction; a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction; a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns; a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns. The gate spacer includes a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns.

公开(公告)号：US20210193654A1

公开(公告)日：2021-06-24

申请号：US16927636

申请日：2020-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Dongil BAE ,  Daewon KIM ,  Taeyoung KIM ,  Joohee JUNG ,  Jaehoon SHIN

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.