公开(公告)号：US11784171B2

公开(公告)日：2023-10-10

申请号：US17696157

申请日：2022-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Inhyo Hwang

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

公开(公告)号：US11329032B2

公开(公告)日：2022-05-10

申请号：US17018324

申请日：2020-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Inhyo Hwang

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

公开(公告)号：US11257793B2

公开(公告)日：2022-02-22

申请号：US16946199

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Young Lyong Kim

IPC: H01L25/065 ,  H01L23/31

Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.

公开(公告)号：US11133232B2

公开(公告)日：2021-09-28

申请号：US16417826

申请日：2019-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang ,  Seung-Duk Baek

IPC: H01L21/66 ,  H01L27/02 ,  G01R31/00 ,  G01R31/28 ,  H02H9/04

Abstract: A semiconductor device is provided. The semiconductor device includes a functional circuit; a plurality of electrostatic discharge (ESD) protection circuits formed independently of the functional circuit, wherein each of the plurality of ESD protection circuits includes a plurality of junctions having different sizes and capacities, each of the plurality of ESD protection circuits is configured to perform an ESD test in different processes of fabrication of the semiconductor device; and a plurality of test pads connected to the plurality of ESD protection circuits and the functional circuit, respectively, wherein each of the plurality of test pads is configured to receive a test signal for the ESD test.

公开(公告)号：US20240153886A1

公开(公告)日：2024-05-09

申请号：US18225447

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haseob Seong ,  Seungduk Baek ,  Ae-Nee Jang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08146

Abstract: A semiconductor package includes a substrate including a substrate pad and plural vias, the substrate having a first trench on a top surface of the substrate, and a chip stack on the substrate that includes semiconductor chips. A chip pad of a first semiconductor chip, which is a lowermost one of the semiconductor chips, is bonded to the substrate pad of the substrate. The chip pad and the substrate pad are formed of a same metallic material. The first trench overlaps with a corner of the first semiconductor chip, when viewed in plan view.

公开(公告)号：US11948919B2

公开(公告)日：2024-04-02

申请号：US17454114

申请日：2021-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/08 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562

Abstract: A semiconductor package includes a plurality of first semiconductor structures that are stacked on a package substrate and are offset from each other in a first direction, and a plurality of first adhesive layers disposed between the first semiconductor structures. Each of the first semiconductor structures includes a first sub-chip and a second sub-chip in contact with a part of a top surface of the first sub-chip. The first adhesive layers are disposed between and are in contact with the first sub-chips. The first adhesive layers are spaced apart from the second sub-chips. A thickness of each of the first adhesive layers is less than a thickness of each of the second sub-chips. The thickness of the second sub-chip is in a range of about 13 μm to about 20 μm.

公开(公告)号：US20240055372A1

公开(公告)日：2024-02-15

申请号：US18315689

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Jihoon Kim ,  Seungduk Baek ,  Hyuekjae Lee

IPC: H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L25/0657 ,  H10B80/00 ,  H01L24/94 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/05647 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1438 ,  H01L2224/94 ,  H01L2224/80895

Abstract: A semiconductor device includes a substrate and a lower die on the substrate. The lower die includes a first semiconductor substrate having a first device region and a first edge region therein, a first semiconductor element on the first device region, a first pad on the first device region and on the first semiconductor element, and a first interconnection structure connecting the first semiconductor element to the first pad. The first interconnection structure includes a first signal pattern on the first device region and connected to the first semiconductor element, a second signal pattern on the first device region and directly connected to the first pad, and a first dummy pattern at the same level as the second signal pattern and disposed on the first edge region. An upper die is provided, which is bonded to the lower die such that the first pad of the lower die is in contact with a second pad of the upper die.

公开(公告)号：US11837577B2

公开(公告)日：2023-12-05

申请号：US17853140

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Kyung Suk Oh ,  Eunseok Song ,  Seung-Yong Cha

IPC: H01L23/528 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L23/528 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

公开(公告)号：US11769746B2

公开(公告)日：2023-09-26

申请号：US17189405

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang ,  KyungSeon Hwang ,  SunWon Kang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L23/481 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/73 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/10125 ,  H01L2224/1147 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/14104 ,  H01L2224/14515 ,  H01L2224/14517 ,  H01L2224/26145 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/01074 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2224/131 ,  H01L2924/014

Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

公开(公告)号：US11664292B2

公开(公告)日：2023-05-30

申请号：US17340197

申请日：2021-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang ,  Seung-Duk Baek ,  Tae-Heon Kim

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/31 ,  H01L23/48 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384

Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.