公开(公告)号：US20160064365A1

公开(公告)日：2016-03-03

申请号：US14626326

申请日：2015-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-GWON JANG ,  Seok-Hyun Lee ,  Ae-Nee Jang

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a package substrate having a lower substrate and an upper substrate disposed on the lower substrate, the package substrate having a first cavity, a first semiconductor chip disposed in the first cavity, and a chip stack disposed to partially cover the first cavity on the upper substrate.

Abstract translation: 半导体封装包括具有下基板和设置在下基板上的上基板的封装基板，封装基板具有第一空腔，设置在第一空腔中的第一半导体芯片和设置成部分地覆盖第一空腔的芯片堆叠 在上基板上。

公开(公告)号：US11056414B2

公开(公告)日：2021-07-06

申请号：US16507974

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang ,  Seung-Duk Baek ,  Tae-Heon Kim

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/31 ,  H01L23/48 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.

公开(公告)号：US20140021593A1

公开(公告)日：2014-01-23

申请号：US13785675

申请日：2013-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Gwon Jang ,  Young-Lyong Kim ,  Ae-Nee Jang

IPC: H01L23/495

CPC classification number: H01L23/49541 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L2224/16

Abstract: A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package.

Abstract translation: 半导体封装可以包括具有通孔的电路板芯片，安装在电路板芯片上的半导体器件和密封剂。 密封剂封装半导体器件，填充通孔并具有作为其中形成密封剂的模具的互补体的外部图案。 包装的一侧上的外部图案反映了模制形状，该模具形状相对于包装材料的相对侧上的密封剂材料流延迟封装材料的流动。

公开(公告)号：US12002731B2

公开(公告)日：2024-06-04

申请号：US17387212

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  In Hyo Hwang

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3735 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: Provided is a semiconductor package including a stiffener. The semiconductor package comprises a circuit board, a semiconductor chip on the circuit board, and a stiffener around the semiconductor chip, wherein the stiffener includes a first metal layer, a core layer, and a second metal layer sequentially stacked.

公开(公告)号：US20240170458A1

公开(公告)日：2024-05-23

申请号：US18471678

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Seung Ji ,  Ha Seob Seong ,  Ae-Nee Jang

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06541 ,  H01L2924/3511

Abstract: A semiconductor package and a method of fabricating the same are provided. The semiconductor package includes a first semiconductor chip; a chip stack including a plurality of second semiconductor chips, which are stacked on the first semiconductor chip; a first molding layer in contact with an upper surface of the first semiconductor chip and side surfaces of the chip stack and exposing an upper surface of the chip stack; a bonding layer in contact with an upper surface of the first molding layer and the upper surface of the chip stack; a dummy semiconductor chip on the bonding layer; and a second molding layer on at least part of the dummy semiconductor chip and on the bonding layer, wherein the upper surface of the chip stack has a wavy shape, and an upper surface of the bonding layer is flat.

公开(公告)号：US11869775B2

公开(公告)日：2024-01-09

申请号：US18169161

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/485 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/73 ,  H01L21/60 ,  H01L2224/023 ,  H01L2224/0508 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US11776866B2

公开(公告)日：2023-10-03

申请号：US16994938

申请日：2020-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shle-Ge Lee ,  Youngbae Kim ,  Ae-Nee Jang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L23/528 ,  H01L24/14 ,  H01L25/0655 ,  H01L2224/73253

Abstract: A semiconductor module includes a substrate having a central region, an outer region that surrounds the central region, and a middle region disposed between the central and the outer region, a first semiconductor package mounted on the central region of the substrate, a plurality of second semiconductor packages mounted on the middle region of the substrate, and a heat radiation structure disposed on the first semiconductor package and second semiconductor packages. The heat radiation structure includes a first part that is disposed on top surfaces of the first and second semiconductor packages, a second part that surrounds the middle region, a third part that is spaced apart from the second part and surrounds the first semiconductor package, and a fourth part that connects the second part to the third part.

公开(公告)号：US20230197469A1

公开(公告)日：2023-06-22

申请号：US18169161

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/485 ,  H01L21/60

CPC classification number: H01L21/563 ,  H01L24/73 ,  H01L24/13 ,  H01L24/05 ,  H01L23/49816 ,  H01L23/485 ,  H01L2224/05548 ,  H01L2224/05022 ,  H01L2924/15311 ,  H01L21/60 ,  H01L2224/13024 ,  H01L2224/0508 ,  H01L2224/73204 ,  H01L2224/023

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US11955399B2

公开(公告)日：2024-04-09

申请号：US18137803

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang ,  Seung-Duk Baek ,  Tae-Heon Kim

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384

Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.

公开(公告)号：US11830853B2

公开(公告)日：2023-11-28

申请号：US17582079

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Young Lyong Kim

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L25/0652 ,  H01L2224/09181 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562

Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.