公开(公告)号：US20140175642A1

公开(公告)日：2014-06-26

申请号：US14192706

申请日：2014-02-27

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电焊盘。 通过在第一导电焊盘中形成多个凹槽来扩展第一导电焊盘的互连表面积。 凹槽可以是同心环的布置，圆形凹槽的布置或平行的线性沟槽的布置。 或者，通过在第一导电焊盘上形成第二导电焊盘来扩展第一导电焊盘的互连表面积。 半导体管芯具有在半导体管芯的表面上形成的多个互连结构。 半导体管芯安装到衬底上，互连结构接触第一导电焊盘的扩展互连表面区域，以增加互连结构与第一导电焊盘的接合强度。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US08709935B2

公开(公告)日：2014-04-29

申请号：US13768862

申请日：2013-02-15

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L21/44 ,  H01L21/50 ,  H01L23/52 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电焊盘。 通过在第一导电焊盘中形成多个凹槽来扩展第一导电焊盘的互连表面积。 凹槽可以是同心环的布置，圆形凹槽的布置或平行的线性沟槽的布置。 或者，通过在第一导电焊盘上形成第二导电焊盘来扩展第一导电焊盘的互连表面积。 半导体管芯具有形成在半导体管芯的表面上的多个互连结构。 半导体管芯安装到衬底上，互连结构接触第一导电焊盘的扩展互连表面区域，以增加互连结构与第一导电焊盘的接合强度。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US08884339B2

公开(公告)日：2014-11-11

申请号：US13906844

申请日：2013-05-31

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

IPC: H01L23/48

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

Abstract translation: 一种具有倒装芯片半导体管芯和衬底的半导体器件。 在衬底上形成第一绝缘层。 通过第一绝缘层形成通孔。 导电材料沉积在通孔中以形成导电柱或堆叠的柱状凸块。 导电柱与衬底内的导电层电连接。 在第一绝缘层上形成第二绝缘层。 凸起材料形成在导电柱上。 凸块材料被回流以形成凸块。 去除第一和第二绝缘层。 半导体管芯通过将凸块回流到管芯的导电层而安装到衬底上。 半导体管芯还具有形成在导电层上的第三绝缘层和形成在第一导电层和第三绝缘层上的管芯和UBM的有源表面。

公开(公告)号：US20130087913A1

公开(公告)日：2013-04-11

申请号：US13691427

申请日：2012-11-30

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

IPC: H01L23/498

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.