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    STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF
    11.
    发明申请
    STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF 审中-公开

    公开(公告)号：US20200176563A1

    公开(公告)日：2020-06-04

    申请号：US16781856

    申请日：2020-02-04

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM

    IPC: H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532

    Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

    LOW-AREA LOW CLOCK-POWER FLIP-FLOP
    13.
    发明申请
    LOW-AREA LOW CLOCK-POWER FLIP-FLOP 有权

    公开(公告)号：US20170257080A1

    公开(公告)日：2017-09-07

    申请号：US15061055

    申请日：2016-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Seid Hadi RASOULI ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI

    IPC: H03K3/012 ,  H03K3/356

    CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/35625

    Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

    INTEGRATED POWER MANAGEMENT CELLS FOR GATE ALL AROUND TECHNOLOGIES
    14.
    发明申请
    INTEGRATED POWER MANAGEMENT CELLS FOR GATE ALL AROUND TECHNOLOGIES 有权

    公开(公告)号：US20250150080A1

    公开(公告)日：2025-05-08

    申请号：US18504062

    申请日：2023-11-07

    Applicant: QUALCOMM Incorporated

    Inventor： Ramaprasath VILANGUDIPITCHAI ,  Venkat NARAYANAN ,  Giby SAMSON ,  Venugopal BOYNAPALLI

    IPC: H03K19/0185 ,  H03K3/012 ,  H03K3/356

    Abstract: At least one integrated power management cell of an IC includes a first cell, which is a 4-height cell, that includes a first continuous n-well, a first power interconnect coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well, a second continuous n-well, a second power interconnect coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well, a first subset of a first voltage level shifter associated with the first voltage domain and coupled to the first power interconnect, and a second subset of the first voltage level shifter associated with the second voltage domain and coupled to the second power interconnect.

    HETEROGENEOUS HEIGHT LOGIC CELL ARCHITECTURE
    16.
    发明申请
    HETEROGENEOUS HEIGHT LOGIC CELL ARCHITECTURE 有权

    公开(公告)号：US20220115405A1

    公开(公告)日：2022-04-14

    申请号：US17065746

    申请日：2020-10-08

    Applicant: QUALCOMM Incorporated

    Inventor： Hyeokjin LIM ,  Venugopal BOYNAPALLI ,  Foua VANG ,  Seung Hyuk KANG

    IPC: H01L27/118

    Abstract: A MOS IC includes first and second sets of adjacent transistor logic, each of which include collinear gate interconnects extending in a first direction with the same gate pitch. The first set of transistor logic has a first cell height h1 and a first number of Mx layer tracks that extend unidirectionally in a second direction orthogonal to the first direction. The second set of transistor logic has a second cell height h2 and a second number of Mx layer tracks that extend unidirectionally in the second direction, where h2>h1 and the second number of Mx layer tracks is greater than the first number of Mx layer tracks. At least one of a height ratio hR=h2/h1 is a non-integer value or a subset of the first set of transistor logic and a subset of the second set of transistor logic are within one logic cell.

    PULSE-GENERATOR
    18.
    发明申请
    PULSE-GENERATOR 有权

    公开(公告)号：US20170237434A1

    公开(公告)日：2017-08-17

    申请号：US15044988

    申请日：2016-02-16

    Applicant: QUALCOMM Incorporated

    Inventor： Qi YE ,  Animesh DATTA ,  Venkatasubramanian NARAYANAN ,  Venugopal BOYNAPALLI

    IPC: H03K19/003 ,  H03K3/037

    CPC classification number: H03K19/00384 ,  H03K3/033 ,  H03K3/0375 ,  H03K5/04

    Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

    LOW-POWER MEMORY
    20.
    发明申请
    LOW-POWER MEMORY 审中-公开

    公开(公告)号：US20200335151A1

    公开(公告)日：2020-10-22

    申请号：US16849616

    申请日：2020-04-15

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin JUNG ,  Keejong KIM ,  Changho JUNG ,  Venugopal BOYNAPALLI

    IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/408

    Abstract: A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. Prior to the charge-transfer period, a bitcell is coupled to the bit line to drive a bitcell-effected voltage on to the bit line. The charge-transfer driver drives the gate voltage such that the charge-transfer transistor only conducts when the bitcell-effected voltage equals a pre-charge voltage for the bit line.

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