公开(公告)号：US20170062439A1

公开(公告)日：2017-03-02

申请号：US15347530

申请日：2016-11-09

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L23/528 ,  G11C11/419 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L27/1104 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  H01L21/3213 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11

Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

Abstract translation: 一种装置包括耦合到位单元的第一金属层。 该装置还包括第三金属层，其包括耦合到位单元的写入字线。 该装置还包括在第一金属层和第三金属层之间的第二金属层。 第二金属层包括耦合到位单元的两个读字线。

公开(公告)号：US09424909B1

公开(公告)日：2016-08-23

申请号：US14659937

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/417 ,  G06F17/50 ,  G11C11/412

CPC classification number: G11C11/417 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/54 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

Abstract translation: 所公开的方面包括在多种操作模式下具有基本恒定的操作成品率的静态随机存取存储器（SRAM）阵列。 在一个方面，提供了一种设计具有多种模式操作的SRAM阵列的方法。 该方法包括确定与每个操作模式相关联的性能特征。 配置为在每个操作模式下操作的SRAM位单元被提供给SRAM阵列。 SRAM位单元被偏置以在使用动态自适应辅助技术的操作模式下操作，其中SRAM位单元在整个模式下实现基本上恒定的运行产量。 SRAM位单元具有相应的类型，其中方法中的SRAM位单元类型的数量小于操作模式的数量。 因此，每个SRAM阵列可以实现特定的操作模式，而不需要用于每个模式的单独的SRAM位单元类型，从而降低成本。

公开(公告)号：US08969166B2

公开(公告)日：2015-03-03

申请号：US14156785

申请日：2014-01-16

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Choh fei Yeap ,  Ping Liu

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/7833 ,  Y02D70/00

Abstract: An apparatus for selectively improving integrated circuit performance is provided. In an example, an integrated circuit is fabricated according to an integrated circuit layout. A critical portion of the integrated circuit layout determines a speed of the integrated circuit, where at least a part of the critical portion includes at least one of a halo implant region, lightly doped drain (LDD) implant region, and source drain extension (SDE) implant region. A marker layer comprises the part of the critical portion that includes the at least one of the halo implant region, the lightly doped drain (LDD) implant region, and the source drain extension (SDE) implant region, and includes at least one transistor formed therefrom.

Abstract translation: 提供了一种用于选择性地提高集成电路性能的装置。 在一个示例中，根据集成电路布局制造集成电路。 集成电路布局的关键部分确定集成电路的速度，其中临界部分的至少一部分包括光晕注入区域，轻掺杂漏极（LDD）注入区域和源极漏极延伸（SDE）中的至少一个 ）植入区域。 标记层包括关键部分的包括所述卤素注入区，轻掺杂漏极（LDD）注入区和源极漏极延伸（SDE）注入区）中的至少一个的部分，并且包括形成的至少一个晶体管 由此。