公开(公告)号：US09653466B2

公开(公告)日：2017-05-16

申请号：US14817441

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Yanxiang Liu

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7845

Abstract: A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element.

公开(公告)号：US09653281B2

公开(公告)日：2017-05-16

申请号：US14746606

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Yanxiang Liu

IPC: H01L27/02 ,  H01L21/02 ,  G05B19/418 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L21/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/785

Abstract: In a particular aspect, an integrated circuit includes a first gate structure coupled to a first fin field effect transistor (FinFET) device. The integrated circuit includes a second gate structure coupled to a second FinFET device. The first gate structure and the second gate structure are separated by a dielectric region. The integrated circuit further includes a metal contact having a first surface that is in contact with the dielectric region, the first gate structure, and the second gate structure.

公开(公告)号：US10181403B2

公开(公告)日：2019-01-15

申请号：US15910929

申请日：2018-03-02

Applicant: QUALCOMM Incorporated

Inventor： Da Yang ,  Yanxiang Liu ,  Jun Yuan ,  Kern Rim

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US09978738B2

公开(公告)日：2018-05-22

申请号：US15582770

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang

IPC: H01L27/02 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

公开(公告)号：US09607988B2

公开(公告)日：2017-03-28

申请号：US14611090

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Stanley Seungchul Song

IPC: H01L21/70 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207 ,  H01L29/0847

Abstract: A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.

公开(公告)号：US09997360B2

公开(公告)日：2018-06-12

申请号：US15271867

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Da Yang ,  Yanxiang Liu ,  Jun Yuan ,  Kern Rim

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US09853112B2

公开(公告)日：2017-12-26

申请号：US14802479

申请日：2015-07-17

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/538 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  G06F17/50 ,  H01L21/8238 ,  H01L21/304 ,  H01L27/02

CPC classification number: H01L29/4238 ,  G06F17/5077 ,  H01L21/3043 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

Abstract: A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.

公开(公告)号：US20170074728A1

公开(公告)日：2017-03-16

申请号：US14856004

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Kern Rim

IPC: G01K7/01 ,  H01L27/092

CPC classification number: G01K7/015 ,  H01L27/0924 ,  H01L29/78606

Abstract: A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).

Abstract translation: 器件包括源极接触，漏极接触，栅极接触和身体接触。 身体接触件电耦合到温度感测电路。 源极触点，漏极接触，栅极接触和主体接触包括在鳍状场效应晶体管（finFET）中。

公开(公告)号：US09570442B1

公开(公告)日：2017-02-14

申请号：US15133832

申请日：2016-04-20

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Jun Yuan

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649

Abstract: Aspects for applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure are disclosed. In one aspect, a FinFET-based circuit is provided. The FinFET-based circuit includes a semiconductor substrate and a Fin formed from the semiconductor substrate. The FinFET-based circuit also includes first and second FinFETs, each corresponding to the Fin. The FinFET-based circuit also includes a gate region disposed between the first FinFET and the second FinFET. An SDB isolation structure is formed in the Fin between the first FinFET and the second FinFET. The self-aligned SDB isolation structure is self-aligned with the gate region and electrically isolates the first FinFET and the second FinFET. The self-aligned SDB isolation structure applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET.

Abstract translation: 公开了使用自对准单扩散断裂（SDB）隔离结构将沟道应力施加到鳍状场效应晶体管（FET）（FinFET）的方面。 在一个方面，提供了基于FinFET的电路。 基于FinFET的电路包括半导体衬底和由半导体衬底形成的鳍。 基于FinFET的电路还包括第一和第二FinFET，每个FinFET对应于Fin。 基于FinFET的电路还包括设置在第一FinFET和第二FinFET之间的栅极区域。 在第一FinFET和第二FinFET之间的Fin中形成SDB隔离结构。 自对准SDB隔离结构与栅极区域自对准并且电隔离第一FinFET和第二FinFET。 自对准SDB隔离结构将应力施加到对应于第一FinFET的第一通道和对应于第二FinFET的第二通道。

公开(公告)号：US20170018620A1

公开(公告)日：2017-01-19

申请号：US14802479

申请日：2015-07-17

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L27/092 ,  H01L21/304 ,  H01L29/66 ,  G06F17/50 ,  H01L21/8238

CPC classification number: H01L29/4238 ,  G06F17/5077 ,  H01L21/3043 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

Abstract: A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.

Abstract translation: 一种制造器件的方法包括执行栅极切割以切割栅极线以产生第一栅极区域和第二栅极区域。 该方法还包括沉积导电材料以形成导电跳线结构以连接第一栅区和第二栅区。