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11.发明申请公开(公告)号：US20160020759A1
公开(公告)日：2016-01-21
申请号：US14335681
申请日：2014-07-18
Applicant: QUALCOMM Incorporated
Inventor： Thomas Clark Bryan , Alvin Leng Sun Loke , Stephen Knol , Gregory Francis Lynch , Tin Tin Wee , LuVerne Ray Peterson , Yue Li
IPC: H03K5/15 , H01L23/538
CPC classification number: H03K5/15013 , G06F1/10 , G11C7/22 , H01L23/5384 , H01L23/5389 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/24137 , H01L2224/73267 , H01L2924/15311
Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.
Abstract translation: 提供了芯片到芯片时钟分配的电路。 系统包括第一管芯上的传输时钟树和第二管芯上的接收时钟树。 发送时钟树和接收时钟树是相同的或非常接近相同的，所以发送时钟树上的给定位的插入延迟与对应于给定位的位的插入延迟相同 接收时钟树。 虽然在同一个时钟树中可能存在从位到位的时钟偏差，但是不同芯片上的相应位具有相同的时钟插入延迟。
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公开(公告)号：US09984011B2
公开(公告)日：2018-05-29
申请号：US15368445
申请日：2016-12-02
Applicant: QUALCOMM Incorporated
Inventor： Tin Tin Wee , Thomas Bryan
IPC: G06F13/16 , G11C11/401 , G06F9/445 , G06F13/40 , G06F13/42
CPC classification number: G06F13/1694 , G06F9/44505 , G06F13/4086 , G06F13/4234 , G11C11/401
Abstract: A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the active DRAM.
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公开(公告)号：US09977078B2
公开(公告)日：2018-05-22
申请号：US14339224
申请日：2014-07-23
Applicant: QUALCOMM Incorporated
Inventor： Alvin Leng Sun Loke , Thomas Clark Bryan , Reza Jalilizeinali , Tin Tin Wee , Stephen Robert Knol , LuVerne Ray Peterson
IPC: G06F17/50 , G01R31/3177 , G01R31/3185 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31716 , G01R31/318513
Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.
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公开(公告)号：US20170359053A1
公开(公告)日：2017-12-14
申请号：US15178389
申请日：2016-06-09
Applicant: QUALCOMM Incorporated
Inventor： LuVerne Ray Peterson , Thomas Bryan , Tin Tin Wee
CPC classification number: H03K3/012 , G06F1/32 , H03K3/356113 , H03K5/134 , H03K17/161 , H03K19/0005 , H03K19/0008 , H03K19/0013 , H03K19/00361 , H03K2005/00195 , H04L25/03019
Abstract: A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.
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15.发明授权公开(公告)号：US09767889B1
公开(公告)日：2017-09-19
申请号：US15433814
申请日：2017-02-15
Applicant: QUALCOMM Incorporated
Inventor： Scott Powers , Thomas Bryan , Andrew Tohmc , Subrahmanya Pradeep Morusupalli , Tin Tin Wee , Kenneth Dubowski
IPC: G11C11/40 , G11C11/4096 , G11C11/408 , G11C11/4094 , H01L25/18 , H01L25/065 , H01L23/66 , H03H7/38
CPC classification number: G11C11/4096 , G11C7/1084 , G11C11/4093 , H01L23/66 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2223/6611 , H01L2223/6627 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06506 , H01L2225/06517 , H01L2225/0652 , H01L2225/06586 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H03K19/00346 , H01L2924/00012 , H01L2924/00
Abstract: A die is provided having an unterminated endpoint that capacitively loads its input impedance with a capacitance from capacitor while acting as a receiving endpoint and that isolates its output impedance from the capacitance while acting as a transmitting endpoint.
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Patent Agency Ranking
公开(公告)号：US20160025807A1
公开(公告)日：2016-01-28
申请号：US14339224
申请日：2014-07-23
Applicant: QUALCOMM Incorporated
Inventor： Alvin Leng Sun Loke , Thomas Clark Bryan , Reza Jalilizeinali , Tin Tin Wee , Stephen Robert Knol , LuVerne Ray Peterson
IPC: G01R31/3177
CPC classification number: G01R31/3177 , G01R31/31716 , G01R31/318513
Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.
Abstract translation: 提供了用于环回测试的电路和方法。 一个管芯将每个发射器（TX）的接收器（RX）以及每个接收器的TX都包含在内。 该架构被应用于每个位，因此，例如，在操作期间发送或接收32个数据位的管芯将具有32个收发器（每个位一个）。 专注于收发器之一，环回架构包括TX数据路径和RX数据路径，其通过诸如收发器之间的通孔的外部接点相互耦合。 芯片还包括馈送TX数据路径的发射时钟树和馈送RX数据路径的接收时钟树。 传输时钟树通过露出在芯片表面上的导电时钟节点馈送接收时钟树。 一些系统还包括时钟路径中的可变延迟。
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公开(公告)号：US20170351625A1
公开(公告)日：2017-12-07
申请号：US15368445
申请日：2016-12-02
Applicant: QUALCOMM Incorporated
Inventor： Tin Tin Wee , Thomas Bryan
IPC: G06F13/16 , G11C11/401 , G06F9/445
CPC classification number: G06F13/1694 , G06F9/44505 , G06F13/4086 , G06F13/4234 , G11C11/401
Abstract: A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the active DRAM.
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公开(公告)号：US20170134191A1
公开(公告)日：2017-05-11
申请号：US15412631
申请日：2017-01-23
Applicant: QUALCOMM INCORPORATED
Inventor： Mohammed Mizanur Rahman , Thomas Clark Bryan , Jacob Stephen Schneider , Luverne Ray Peterson , Tin Tin Wee , Alvin Leng Sun Loke
CPC classification number: H04L25/03885 , H04B1/16 , H04L25/0278 , H04L25/029 , H04L25/0292 , H04L25/0298 , H04L25/03 , H04L25/03834 , H04L25/03878 , H04L25/08
Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but- for the equalizer.
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公开(公告)号：US09614703B2
公开(公告)日：2017-04-04
申请号：US14852088
申请日：2015-09-11
Applicant: QUALCOMM Incorporated
Inventor： Mohammed Mizanur Rahman , Thomas Clark Bryan , Jacob Stephen Schneider , LuVerne Ray Peterson , Tin Tin Wee , Alvin Leng Sun Loke
CPC classification number: H04L25/03885 , H04B1/16 , H04L25/0278 , H04L25/029 , H04L25/0292 , H04L25/0298 , H04L25/03 , H04L25/03834 , H04L25/03878 , H04L25/08
Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.
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公开(公告)号：US20160308519A1
公开(公告)日：2016-10-20
申请号：US15138142
申请日：2016-04-25
Applicant: QUALCOMM Incorporated
Inventor： Thomas Clark Bryan , Alvin Leng Sun Loke , Stephen Knol , Gregory Francis Lynch , Tin Tin Wee , LuVerne Ray Peterson , Yue Li
IPC: H03K5/15 , H01L23/538 , H01L25/065
CPC classification number: H03K5/15013 , G06F1/10 , G11C7/22 , H01L23/5384 , H01L23/5389 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/24137 , H01L2224/73267 , H01L2924/15311
Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.
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