公开(公告)号：US09767889B1

公开(公告)日：2017-09-19

申请号：US15433814

申请日：2017-02-15

Applicant: QUALCOMM Incorporated

Inventor： Scott Powers ,  Thomas Bryan ,  Andrew Tohmc ,  Subrahmanya Pradeep Morusupalli ,  Tin Tin Wee ,  Kenneth Dubowski

IPC: G11C11/40 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  H01L25/18 ,  H01L25/065 ,  H01L23/66 ,  H03H7/38

CPC classification number: G11C11/4096 ,  G11C7/1084 ,  G11C11/4093 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06586 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K19/00346 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A die is provided having an unterminated endpoint that capacitively loads its input impedance with a capacitance from capacitor while acting as a receiving endpoint and that isolates its output impedance from the capacitance while acting as a transmitting endpoint.

公开(公告)号：US11169940B2

公开(公告)日：2021-11-09

申请号：US16736542

申请日：2020-01-07

Applicant: QUALCOMM Incorporated

Inventor： Sunil Gupta ,  Scott Powers

IPC: G06F13/16 ,  H05K1/18 ,  H05K1/02 ,  G06F3/06

Abstract: A wireline communications system is described. The wireline communications system includes a printed circuit board (PCB). The wireline communications system also includes a system on chip (SoC) die on the PCB. The wireline communications system further includes an external memory device coupled to a memory interface of the SoC die. The external memory device is coupled to the memory interface of the SoC die through a PCB trace. A length of the PCB trace is configured according to an operating speed of the memory interface.