公开(公告)号：US09412818B2

公开(公告)日：2016-08-09

申请号：US14100489

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/22 ,  H01L21/8234

CPC classification number: H01L29/0684 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66795 ,  H01L29/785

Abstract: An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a second FinFET device extending from a surface of a second etch stop layer. A first compound layer is interposed between the first etch stop layer and the second etch stop layer.

Abstract translation: 一种装置包括从第一蚀刻停止层的表面延伸的第一鳍状场效应晶体管（FinFET）器件。 该装置还包括从第二蚀刻停止层的表面延伸的第二FinFET器件。 第一化合物层介于第一蚀刻停止层和第二蚀刻停止层之间。

公开(公告)号：US09076775B2

公开(公告)日：2015-07-07

申请号：US14017635

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Ming Cai ,  Samit Sengupta ,  Chock Hing Gan ,  PR Chidambaram

IPC: H01L27/088 ,  H01L21/70 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/28 ,  G06F17/50 ,  H01L21/66

CPC classification number: H01L27/088 ,  G06F17/5068 ,  H01L21/28035 ,  H01L21/823456 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0207 ,  H01L29/4916

Abstract: A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core.

Abstract translation: 一种方法包括形成第一晶体管的第一多晶硅栅极，第一多晶硅栅极具有第一长度。 第一晶体管位于第一芯中。 该方法还包括形成第二晶体管的第二多晶硅栅极，第二多晶硅栅极具有比第一长度短的第二长度。 第二晶体管位于第二核心中。 第一芯位于比第二芯更靠近半导体晶粒的中心的位置。

公开(公告)号：US20150091060A1

公开(公告)日：2015-04-02

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  PR Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间

公开(公告)号：US09461040B2

公开(公告)日：2016-10-04

申请号：US14792363

申请日：2015-07-06

Applicant: QUALCOMM Incorporated

Inventor： Ming Cai ,  Samit Sengupta ,  Chock Hing Gan ,  PR Chidambaram

IPC: H01L21/00 ,  H01L21/66 ,  H01L27/00 ,  H01L29/00 ,  G06F17/50 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/088 ,  G06F17/5068 ,  H01L21/28035 ,  H01L21/823456 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0207 ,  H01L29/4916

Abstract: A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.

Abstract translation: 一种方法包括形成第一晶体管的第一栅极，第一栅极具有第一长度。 第一晶体管位于第一芯中。 该方法还包括形成第二晶体管的第二栅极，第二栅极具有比第一长度短的第二长度。 第二晶体管位于第二核心中。 第一芯位于比第二芯更靠近半导体晶粒的中心的位置。 第二晶体管和第一晶体管是相应的晶体管。

公开(公告)号：US20150311198A1

公开(公告)日：2015-10-29

申请号：US14792363

申请日：2015-07-06

Applicant: QUALCOMM INCORPORATED

Inventor： Ming Cai ,  Samit Sengupta ,  Chock Hing Gan ,  PR Chidambaram

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  G06F17/5068 ,  H01L21/28035 ,  H01L21/823456 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0207 ,  H01L29/4916

Abstract: A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.

Abstract translation: 一种方法包括形成第一晶体管的第一栅极，第一栅极具有第一长度。 第一晶体管位于第一芯中。 该方法还包括形成第二晶体管的第二栅极，第二栅极具有比第一长度短的第二长度。 第二晶体管位于第二核心中。 第一芯位于比第二芯更靠近半导体晶粒的中心的位置。 第二晶体管和第一晶体管是相应的晶体管。

公开(公告)号：US20150162405A1

公开(公告)日：2015-06-11

申请号：US14100760

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/1045 ,  H01L21/743 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: An apparatus comprises a substrate. The apparatus also comprises a diffusion barrier formed on a surface of a first region of the substrate. The diffusion barrier is formed using a first material having a first band gap energy. The apparatus further comprises a channel region formed on a surface of the diffusion barrier. The channel region is formed using a second material having a second band gap energy that is lower than the first band gap energy. The apparatus further comprises a back gate contact coupled to the first region of the substrate.

Abstract translation: 一种装置包括基板。 该装置还包括形成在基板的第一区域的表面上的扩散阻挡层。 使用具有第一带隙能量的第一材料形成扩散阻挡层。 该装置还包括形成在扩散阻挡层的表面上的沟道区。 沟道区域使用具有低于第一带隙能量的第二带隙能量的第二材料形成。 该装置还包括耦合到衬底的第一区域的背栅极接触。

公开(公告)号：US09024418B2

公开(公告)日：2015-05-05

申请号：US13829864

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Giridhar Nallapati ,  PR Chidambaram

IPC: H01L27/02 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L23/528 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect.

Abstract translation: 提供局部互连结构，其包括通过扩散导向的局部互连耦合到相邻栅极层的栅极定向局部互连。

公开(公告)号：US09012966B2

公开(公告)日：2015-04-21

申请号：US13684059

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： PR Chidambaram ,  Bin Yang

IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.

Abstract translation: 一种用于制造金属 - 绝缘体 - 金属（MIM）电容的方法，包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中间线（MOL）导电层。 第一MOL导电层提供MIM电容器的第一板以及到半导体器件的源极和漏极区域的第一组局部互连。 该方法还包括在第一MOL导电层上沉积绝缘体层作为MIM电容器的电介质层。 所述方法还包括在所述绝缘体层上沉积作为所述MIM电容器的第二板的第二MOL导电层。

公开(公告)号：US20150061037A1

公开(公告)日：2015-03-05

申请号：US14017635

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Ming Cai ,  Samit Sengupta ,  Chock Hing Gan ,  PR Chidambaram

IPC: H01L29/49 ,  G06F17/50 ,  H01L21/66 ,  H01L21/28

CPC classification number: H01L27/088 ,  G06F17/5068 ,  H01L21/28035 ,  H01L21/823456 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0207 ,  H01L29/4916

Abstract: A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core.

Abstract translation: 一种方法包括形成第一晶体管的第一多晶硅栅极，第一多晶硅栅极具有第一长度。 第一晶体管位于第一芯中。 该方法还包括形成第二晶体管的第二多晶硅栅极，第二多晶硅栅极具有比第一长度短的第二长度。 第二晶体管位于第二核心中。 第一芯位于比第二芯更靠近半导体晶粒的中心的位置。

公开(公告)号：US20140264610A1

公开(公告)日：2014-09-18

申请号：US13799955

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/7624 ,  H01L21/765 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/785

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

Abstract translation: 在详细描述中公开的实施例包括具有由伪栅极分开的连续有效区域的金属氧化物半导体（MOS）隔离方案。 MOS器件包括由具有作为n金属或p金属的功函数的材料形成的有源区域。 使用具有类似功函数的材料在该有效区域上形成活性组分。 通过在有源部件之间定位一个虚拟栅极来实现隔离。 虚拟门由相对于有源区的材料具有相反功函数的材料制成。 例如，如果有源区域是p金属材料，则虚拟栅极将由n金属制成，反之亦然。