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    DYNAMIC TAG COMPARE CIRCUITS EMPLOYING P-TYPE FIELD-EFFECT TRANSISTOR (PFET)-DOMINANT EVALUATION CIRCUITS FOR REDUCED EVALUATION TIME, AND RELATED SYSTEMS AND METHODS
    11.
    发明申请
    DYNAMIC TAG COMPARE CIRCUITS EMPLOYING P-TYPE FIELD-EFFECT TRANSISTOR (PFET)-DOMINANT EVALUATION CIRCUITS FOR REDUCED EVALUATION TIME, AND RELATED SYSTEMS AND METHODS 有权
    使用P型场效应晶体管（PFET）的动态标记比较电路降低评估时间的-DOMINANT评估电路及相关系统和方法

    公开(公告)号：US20160247568A1

    公开(公告)日：2016-08-25

    申请号：US14860844

    申请日：2015-09-22

    Applicant: QUALCOMM Incorporated

    Inventor： Keith Alan Bowman ,  Francois Ibrahim Atallah ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

    IPC: G11C15/04 ,  H03K19/003 ,  G11C11/40 ,  H03K19/094

    CPC classification number: G11C15/04 ,  G11C11/40 ,  H03K19/00315 ,  H03K19/094

    Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

    Abstract translation: 提供了采用P型场效应晶体管（PFET）的主要评估电路的动态标签比较电路，用于降低评估时间，从而提高电路性能。 动态标签比较电路可以作为可搜索存储器的一部分使用或提供，例如寄存器文件或内容可寻址存储器（CAM），作为非限制性示例。 动态标签比较电路包括由用作执行比较逻辑功能的逻辑的一个或多个PFET组成的一个或多个PFET主导评估电路。 PFET主导评估电路被配置为接收并将输入搜索数据与包含在可搜索存储器中的标签（例如，地址或数据）进行比较，以确定输入搜索数据是否包含在存储器中。 PFET主导评估电路被配置为基于对所接收的输入搜索数据是否包含在可搜索存储器中的评估来控制动态标签比较电路中的动态节点上的电压/值。

    NEGATIVE SUPPLY RAIL POSITIVE BOOST WRITE-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) WRITE PORT(S), AND RELATED SYSTEMS AND METHODS
    12.
    发明申请
    NEGATIVE SUPPLY RAIL POSITIVE BOOST WRITE-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) WRITE PORT(S), AND RELATED SYSTEMS AND METHODS 有权
    使用P型场效应晶体管（PFET）写入端口（S）的存储器位电池的负电源正向升压写入电路及相关系统和方法

    公开(公告)号：US20160247558A1

    公开(公告)日：2016-08-25

    申请号：US14862636

    申请日：2015-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

    IPC: G11C11/419

    CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C11/413 ,  G11C11/419 ,  G11C15/04

    Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of a negative supply rail positive boost circuit can be employed to weaken an NFET pull-down transistor in a storage circuit of a memory bit cells having a PFET write port(s).

    Abstract translation: 公开了采用P型场效应晶体管（PFET）写入端口的存储器位单元（“位单元”）的写辅助电路。 还公开了相关方法和系统。 已经观察到，随着节点技术的尺寸缩小，PFET驱动电流（即，驱动强度）超过用于等尺寸FET的N型场效应晶体管（NFET）驱动电流。 在这方面，在一个方面，期望提供与NFET写入端口相反的具有PFET写入端口的位单元，以减少对位单元的存储器写入时间，从而提高存储器性能。 为了减轻在将数据写入位单元时可能发生的写入争用，可以采用以负电源正极升压电路形式提供的写辅助电路来削弱存储电路中的NFET下拉晶体管 具有PFET写入端口的存储器位单元。

    Ring oscillator-based programmable delay line
    15.
    发明授权
    Ring oscillator-based programmable delay line 有权

    公开(公告)号：US10587253B1

    公开(公告)日：2020-03-10

    申请号：US16205093

    申请日：2018-11-29

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Huang ,  Nam Dang ,  Keith Alan Bowman ,  Navid Toosizadeh

    IPC: G06F1/04 ,  H03K5/1534 ,  H03K5/135 ,  H03K3/03 ,  H03K21/38 ,  H03K19/20 ,  H03K5/00

    Abstract: A programmable delay line includes a pulse generator configured to generate a pulse in response to a transition of an input signal; an oscillator configured to generate a clock in response to the pulse; a counter configured to change a current count from a first value towards a second value in response to periods of the clock; and a gating device configured to output the transition of the input signal to generate an output signal in response to the current count reaching the second value. The delay of the input signal is a function of the difference between the first value and the second value. The delay line may be used in different applications, such as a dynamic variation monitor (DVM) configured to detect supply voltage droop. The DVM may be in an adaptive clock distribution (ACD) to reduce the clock frequency for a datapath in response to a droop.

    MULTI-PUMP MEMORY SYSTEM ACCESS CIRCUITS FOR SEQUENTIALLY EXECUTING PARALLEL MEMORY OPERATIONS
    17.
    发明申请
    MULTI-PUMP MEMORY SYSTEM ACCESS CIRCUITS FOR SEQUENTIALLY EXECUTING PARALLEL MEMORY OPERATIONS 审中-公开

    公开(公告)号：US20190080737A1

    公开(公告)日：2019-03-14

    申请号：US16126817

    申请日：2018-09-10

    Applicant: QUALCOMM Incorporated

    Inventor： Hoan Huu Nguyen ,  Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman

    IPC: G11C8/16 ,  G06F13/16 ,  G11C8/10 ,  G11C8/08 ,  G11C8/18 ,  G11C8/04

    Abstract: Multi-pump memory system access circuits for sequentially executing parallel memory operations in a memory system are disclosed. A memory system includes a plurality of memory bit cells in a memory array. Each memory bit cell is accessible at a corresponding memory address used by memory read and write operations. The memory system includes ports at which a memory read or a memory write operation is received from a processor in each cycle of a processor clock. To increase memory bandwidth of the memory system without increasing the number of access ports of the memory array within the memory system, a double-pump memory system access circuit double-pumps (i.e., time-multiplexes) the access ports of memory array, effectively doubling the number of ports of the memory array. The double-pump memory system access circuit performs sequential accesses to a port of a memory cell in a memory array within a processor clock period.

    Dynamically adaptive voltage-frequency guardband control circuit
    18.
    发明授权
    Dynamically adaptive voltage-frequency guardband control circuit 有权

    公开(公告)号：US10009016B1

    公开(公告)日：2018-06-26

    申请号：US15393107

    申请日：2016-12-28

    Applicant: QUALCOMM Incorporated

    Inventor： Lam Ho ,  Keith Alan Bowman ,  Navid Toosizadeh ,  Shih-Hsin Jason Hu ,  Mohammad Reza Kakoee ,  Saravana Krishnan Kannan

    IPC: G01R31/00 ,  G01R19/00 ,  H03K5/05 ,  H03K5/19 ,  H03K5/00

    Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.

    Systems and methods for adaptive clock design
    20.
    发明授权
    Systems and methods for adaptive clock design 有权

    公开(公告)号：US09915968B2

    公开(公告)日：2018-03-13

    申请号：US15133068

    申请日：2016-04-19

    Applicant: QUALCOMM Incorporated

    Inventor： Palkesh Jain ,  Virendra Bansal ,  Manoj Mehrotra ,  Keith Alan Bowman

    IPC: G06F1/04 ,  G06F1/26 ,  H03K3/03 ,  H03L7/06

    CPC classification number: G06F1/04 ,  G06F1/08 ,  G06F1/26 ,  G06F1/305 ,  H03K3/0315 ,  H03L7/06

    Abstract: The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.

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