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    Stacked chip package structure and manufacturing method thereof
    13.
    发明授权
    Stacked chip package structure and manufacturing method thereof 有权

    公开(公告)号：US10950557B2

    公开(公告)日：2021-03-16

    申请号：US16780921

    申请日：2020-02-04

    Applicant: Powertech Technology Inc.

    Inventor： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

    IPC: H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

    Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    14.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200013721A1

    公开(公告)日：2020-01-09

    申请号：US16030826

    申请日：2018-07-09

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Wen-Jeng Fan

    IPC: H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/367 ,  H01L23/552 ,  H01L21/683

    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a conductive casing, a semiconductor die, a conductive connector, an insulating encapsulant, a redistribution structure, and a first conductive terminal. The conductive casing has a cavity. The semiconductor die is disposed in the cavity of the conductive casing. The conductive connector is disposed on a periphery of the conductive casing. The insulating encapsulant encapsulates the conductive connector, the semiconductor die and the cavity. The redistribution structure is formed on the insulating encapsulant and is electrically connected to the conductive connector and the semiconductor die. The first conductive terminal is disposed in openings of the redistribution structure and is physically in contact with a portion of the conductive casing.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    15.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200006274A1

    公开(公告)日：2020-01-02

    申请号：US16022707

    申请日：2018-06-29

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Wen-Jeng Fan

    IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/48

    Abstract: A semiconductor package includes a semiconductor die, a first redistribution structure, a conductive structure, and an insulating encapsulant. The first redistribution structure includes a dielectric protrusion. The first redistribution structure includes a die attach region and a peripheral region surrounding the die attach region. The semiconductor die is disposed on the first redistribution structure within the die attach region. The dielectric protrusion is disposed in the peripheral region and extends in a thickness direction of the semiconductor die. The conductive structure is disposed on the first redistribution structure within the in the peripheral region and encapsulates the semiconductor dielectric protrusion. The conductive structure is electrically coupled to the first redistribution structure and the semiconductor die. The insulator is disposed on the first redistribution structure and encapsulates the semiconductor die and the conductive structure.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    16.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190214347A1

    公开(公告)日：2019-07-11

    申请号：US15867670

    申请日：2018-01-10

    Applicant: Powertech Technology Inc.

    Inventor： Chien-Wen Huang ,  Chia-Wei Chiang ,  Wen-Jeng Fan ,  Li-Chih Fang

    IPC: H01L23/538 ,  H01L25/10 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

    Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

    MANUFACTURING METHOD OF CHIP PACKAGE STRUCTURE
    17.
    发明申请
    MANUFACTURING METHOD OF CHIP PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20190051626A1

    公开(公告)日：2019-02-14

    申请号：US16164811

    申请日：2018-10-19

    Applicant: Powertech Technology Inc.

    Inventor： Li-Chih Fang ,  Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

    IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498

    Abstract: A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer.

    Chip package structure comprising encapsulant having concave surface
    18.
    发明授权
    Chip package structure comprising encapsulant having concave surface 有权

    公开(公告)号：US10163834B2

    公开(公告)日：2018-12-25

    申请号：US15600804

    申请日：2017-05-22

    Applicant: Powertech Technology Inc.

    Inventor： Li-Chih Fang ,  Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/538

    Abstract: A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. The encapsulant encapsulates the chip and exposes active surface, wherein the encapsulant includes a concave surface and a back surface opposite to the concave surface, the concave surface exposes the active surface and is dented toward the back surface. The dielectric layer covers the concave surface and the active surface and includes a plurality of openings exposing the pads, wherein the opening includes a slanted side surface and the angle between the slanted side surface and the active surface is an acute angle. The patterned circuit layer is disposed on the dielectric layer and electrically connected to the pads through the openings.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    20.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200243461A1

    公开(公告)日：2020-07-30

    申请号：US16261561

    申请日：2019-01-30

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Wen-Jeng Fan

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a bumpless die including a plurality of conductive pads, a conductive connector disposed aside the bumpless die and electrically coupled to the bumpless die, an insulating encapsulation encapsulating the bumpless die and the conductive connector, a circuit layer electrically connected to the bumpless die and the conductive connector, and a front side redistribution layer disposed on the circuit layer and including a finer line and spacing routing than the circuit layer. The circuit layer includes a conductive pattern disposed on the insulating encapsulation and extending along a thickness direction of the bumpless die to be connected to the conductive pads of the bumpless die, and a dielectric pattern disposed on the insulating encapsulation and laterally covering the conductive pattern.

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