公开(公告)号：US20220254902A1

公开(公告)日：2022-08-11

申请号：US17626055

申请日：2020-06-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki OKITA ,  Masahiro HIKITA ,  Manabu YANAGIHARA

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A nitride semiconductor device includes a semiconductor layered structure including a substrate, a channel layer, and a barrier layer. The channel layer is formed above the substrate and made of a nitride semiconductor layer. The barrier layer is formed on the channel layer, has a wider band gap than the channel layer, and is made of a nitride semiconductor layer. The semiconductor layered structure includes an isolation region in which impurities are implanted. The position of an impurity concentration peak in the depth direction in the isolation region is deeper than the interface between the barrier layer and the channel layer. The concentration of the impurities at the interface between the barrier layer and the channel layer in the isolation region is lower than the concentration at the impurity concentration peak.

公开(公告)号：US20180040706A1

公开(公告)日：2018-02-08

申请号：US15728141

申请日：2017-10-09

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Saichirou KANEKO ,  Hiroto YAMAGIWA ,  Ayanori IKOSHI ,  Masayuki KURODA ,  Manabu YANAGIHARA ,  Kenichiro TANAKA ,  Tetsuyuki FUKUSHIMA

IPC: H01L29/47 ,  H01L29/778 ,  H01L29/205 ,  H01L21/28 ,  H01L29/20 ,  H01L29/10 ,  H01L29/872 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/475 ,  H01L21/28 ,  H01L29/0619 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

公开(公告)号：US20160351676A1

公开(公告)日：2016-12-01

申请号：US15234775

申请日：2016-08-11

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Saichirou KANEKO ,  Hiroto YAMAGIWA ,  Ayanori IKOSHI ,  Masayuki KURODA ,  Manabu YANAGIHARA ,  Kenichiro TANAKA ,  Tetsuyuki FUKUSHIMA

IPC: H01L29/47 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778 ,  H01L29/872

CPC classification number: H01L29/475 ,  H01L21/28 ,  H01L29/0619 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

公开(公告)号：US20230386978A1

公开(公告)日：2023-11-30

申请号：US18248990

申请日：2021-08-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masayuki KURODA ,  Takahiro SATO ,  Manabu YANAGIHARA ,  Hideyuki OKITA ,  Masahiro HIKITA

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L27/02 ,  H01L23/495

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L27/0255 ,  H01L23/4952 ,  H01L23/49562

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; finger-shaped source electrodes on the second nitride semiconductor layer; finger-shaped drain electrodes disposed so as to be spaced apart from the source electrodes; and finger-shaped gate electrodes respectively disposed between the source electrodes and the drain electrodes. The gate electrodes are electrically connected, via a first gate integrated wiring, a plurality of second gate integrated wirings and a third gate integrated wiring, to gate pads located on one or both ends of the third gate integrated wiring. A plurality of source pads and the plurality of second gate integrated wirings are formed alternately in a first direction perpendicular to the longitudinal direction of the gate electrodes.

公开(公告)号：US20230361179A1

公开(公告)日：2023-11-09

申请号：US18246280

申请日：2021-08-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Masayuki KURODA ,  Hiroto YAMAGIWA ,  Hideyuki OKITA ,  Masahiro HIKITA

IPC: H01L29/20 ,  H01L29/417 ,  H01L29/866 ,  H01L23/48 ,  H01L29/861

CPC classification number: H01L29/2003 ,  H01L29/41775 ,  H01L29/866 ,  H01L23/481 ,  H01L29/8613

Abstract: A nitride semiconductor device includes: a first active area surrounded by an isolation area; and the following electrodes above the first active area: a source electrode; a first gate electrode and a second gate electrode, one on either side of and spaced from the source electrode in a first direction in plan view; and at least one drain electrode located in a direction opposite the source electrode relative to the first gate electrode or the second gate electrode. The source electrode, the first gate electrode, the second gate electrode, and the at least one drain electrode each include a finger-shaped portion extending in a second direction perpendicular to the first direction in the plan view. A first dielectric film is disposed above the source electrode. The first gate electrode and the second gate electrode are electrically connected by a gate electrode joiner disposed above the first dielectric film.

公开(公告)号：US20210183747A1

公开(公告)日：2021-06-17

申请号：US17190261

申请日：2021-03-02

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Hidekazu NAKAMURA ,  Manabu YANAGIHARA ,  Tomohiko NAKAMURA ,  Yusuke KATAGIRI ,  Katsumi OTANI ,  Takeshi KAWABATA

IPC: H01L23/495 ,  H01L29/20 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L21/52 ,  H01L23/48

Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0≤x≤1, 0≤y≤1, 0≤x+y ≤1; and a die pad including
Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm ≥2.00×10−3×L2+0.173, tm being a thickness in mm and L being a length in mm.

公开(公告)号：US20170148701A1

公开(公告)日：2017-05-25

申请号：US15427629

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ayanori IKOSHI ,  Masahiro HIKITA ,  Keiichi MATSUNAGA ,  Takahiro SATO ,  Manabu YANAGIHARA

IPC: H01L23/31 ,  H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/291 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/528 ,  H01L23/564 ,  H01L24/05 ,  H01L29/0684 ,  H01L29/417 ,  H01L29/812 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05023 ,  H01L2224/05144 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/48463 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film.

公开(公告)号：US20170098649A1

公开(公告)日：2017-04-06

申请号：US15380642

申请日：2016-12-15

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Takahiro OHORI ,  Chikashi HAYASHI ,  Manabu YANAGIHARA

IPC: H01L27/095 ,  H01L27/098 ,  H01L27/06

CPC classification number: H01L27/095 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/0883 ,  H01L27/098 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/872

Abstract: A semiconductor device includes: a first semiconductor layer stacked body including a compound semiconductor; a first field-effect transistor element including a first drain electrode, a first source electrode, and a first gate electrode that are provided on the first semiconductor layer stacked body; a second semiconductor layer stacked body including a compound semiconductor; and a second field-effect transistor element including a second drain electrode, a second source electrode, and a second gate electrode that are provided on the second semiconductor layer stacked body. The second gate electrode forms a Schottky junction or a p-n junction with the second semiconductor layer stacked body, the second drain electrode is connected to the first drain electrode, the second source electrode is connected to the first gate electrode, and the second gate electrode is connected to the first source electrode.