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公开(公告)号：US11139816B2
公开(公告)日：2021-10-05
申请号：US16822025
申请日：2020-03-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Po-Min Cheng , Wun-Jian Su , Chia-Hui Yu
Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.
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公开(公告)号：US20210273642A1
公开(公告)日：2021-09-02
申请号：US16822025
申请日：2020-03-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Po-Min Cheng , Wun-Jian Su , Chia-Hui Yu
Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.
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公开(公告)号：US11757684B2
公开(公告)日：2023-09-12
申请号：US17543741
申请日：2021-12-07
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chun-Wei Chang , Ching-Jui Hsiao , Jen-Chu Wu , Yuwei Kuo
IPC: H04L25/49
CPC classification number: H04L25/4904
Abstract: A retiming circuit module, a signal transmission system, and a signal transmission method are provided. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes built-in first signal transmission path and second signal transmission path. The multipath signal transmission circuit may perform first signal transmission between an upstream device and a downstream device based on a first signal transmission frequency and the second signal transmission path. During a period of performing the first signal transmission, the path control circuit may detect a first data sequence transmitted between the upstream device and the downstream device. The path control circuit may control the multipath signal transmission circuit to switch to perform second signal transmission between the upstream device and the downstream device based on the first signal transmission frequency and the first signal transmission path according to the first data sequence.
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公开(公告)号：US20210257033A1
公开(公告)日：2021-08-19
申请号：US16805848
申请日：2020-03-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Bo-Jing Lin , Yu-Chiang Liao
Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.
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公开(公告)号：US10297297B2
公开(公告)日：2019-05-21
申请号：US14578471
申请日：2014-12-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Wei-Yung Chen
Abstract: A sampling circuit module, a memory control circuit unit, and a data sampling method, where the sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.
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Patent Agency Ranking
公开(公告)号：US09836121B2
公开(公告)日：2017-12-05
申请号：US14856563
申请日：2015-09-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Wei-Yung Chen , Yu-An Chen
Abstract: An eye-width detector, a memory storage device and an eye-width detection method of data signal are provided. The eye-width detector includes a phase interpolator, a calibration circuit and an eye-width detection circuit. The phase interpolator receives a first clock signal and a phase control signal and output a second clock signal. The calibration circuit receives the first clock signal and the second clock signal and output a first control signal. The eye-width detection circuit receive the data signal, the first clock signal and the second clock signal and generate a first sampling value and a second sampling value. If the first sampling value and the second sampling value do not match a first condition, the eye-width detection circuit outputs a second control signal; otherwise, outputs eye-width information of the data signal. Accordingly, the efficiency of the eye-width detection may be improved.
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17.发明申请EYE-WIDTH DETECTOR, MEMORY STORAGE DEVICE AND EYE-WIDTH DETECTION METHOD OF DATA SIGNAL 有权眼睛宽度检测器，存储器件和数据信号的眼睛宽度检测方法公开(公告)号：US20170031436A1
公开(公告)日：2017-02-02
申请号：US14856563
申请日：2015-09-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Wei-Yung Chen , Yu-An Chen
IPC: G06F3/01
Abstract: An eye-width detector, a memory storage device and an eye-width detection method of data signal are provided. The eye-width detector includes a phase interpolator, a calibration circuit and an eye-width detection circuit. The phase interpolator receives a first clock signal and a phase control signal and output a second clock signal. The calibration circuit receives the first clock signal and the second clock signal and output a first control signal. The eye-width detection circuit receive the data signal, the first clock signal and the second clock signal and generate a first sampling value and a second sampling value. If the first sampling value and the second sampling value do not match a first condition, the eye-width detection circuit outputs a second control signal; otherwise, outputs eye-width information of the data signal. Accordingly, the efficiency of the eye-width detection may be improved.
Abstract translation: 提供了眼宽检测器，存储器存储装置和数据信号的眼宽检测方法。 眼宽检测器包括相位插值器，校准电路和眼睛宽度检测电路。 相位插值器接收第一时钟信号和相位控制信号并输出第二时钟信号。 校准电路接收第一时钟信号和第二时钟信号并输出第一控制信号。 眼宽检测电路接收数据信号，第一时钟信号和第二时钟信号，并产生第一采样值和第二采样值。 如果第一采样值和第二采样值与第一条件不匹配，则眼宽检测电路输出第二控制信号; 否则输出数据信号的眼宽信息。 因此，可以提高眼宽检测的效率。
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18.发明授权Sampling circuit module, memory control circuit unit, and method for sampling data 有权采样电路模块，存储器控制电路单元和数据采样方法公开(公告)号：US09449660B2
公开(公告)日：2016-09-20
申请号：US14309879
申请日：2014-06-19
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , An-Chung Chen
CPC classification number: G11C7/22 , G11C7/1093 , H03L7/0805 , H03L7/0812
Abstract: A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal.
Abstract translation: 提供采样电路模块，存储器控制电路单元和数据采样方法。 采样电路模块包括状态机电路，第一延迟线电路，第二延迟线电路和延迟信号输出电路。 响应于第一控制信号，状态机电路输出第二控制信号和/或第三控制信号。 第一延迟线电路被配置为接收参考时钟信号和第二控制信号以输出第一延迟时钟信号。 第二延迟线电路被配置为接收参考时钟信号和第三控制信号以输出第二延迟时钟信号。 延迟信号输出电路被配置为接收第一延迟时钟信号和第二延迟时钟信号以输出第三延迟时钟信号。
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公开(公告)号：US11636902B2
公开(公告)日：2023-04-25
申请号：US17468711
申请日：2021-09-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Guan-Wei Wu , Jen-Chu Wu , Jen-Huo Wang , Yu-Chiang Liao , Shih-Yang Sun
Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
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公开(公告)号：US20200252258A1
公开(公告)日：2020-08-06
申请号：US16362725
申请日：2019-03-25
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Yu-Chiang Liao
Abstract: A signal calibration circuit including a first phase interpolator, a second phase interpolator, a phase detector, a control circuit and a delay circuit is provided according to an exemplary embodiment of the disclosure. The first phase interpolator is configured to receive a plurality of first signals and generate a plurality of first quadrature signals according to the first signals. The second phase interpolator is configured to generate a second signal according to the first quadrature signals. The phase detector is configured to detect a phase difference between the second signal and one of the first signals. The control circuit is configured to generate a calibration parameter according to the phase difference. The delay circuit is configured to adjust at least one of the first signals according to the calibration parameter, such that the adjusted first signal includes a plurality of second quadrature signals.
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